A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via has a diameter of less than 400 nm and greater than 5 nm.

A 3D semiconductor device including: a first single-crystal layer including a plurality of first transistors; at least one first metal layer disposed atop the plurality of first transistors; a second metal layer disposed atop the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed atop the plurality of fourth transistors; a fourth metal layer disposed atop the third metal layer; a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed on top of the control circuits; performing a first etch step including etching first holes within the second level; and performing additional processing steps (including Atomic Layer Deposition) to form a plurality of memory cells within the second level, where each memory cell includes at least one second transistor, where making the second level includes forming lithography holes atop of the first alignment marks which enables performing lithography steps aligned to the first alignment marks, including at least the first etch step above.

A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step.

A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.

A switching module includes a substrate, a switching element, a first control part, a second control part, a first power part and a second power part. The switching element is disposed on the substrate. The switching element includes a first control terminal, a second control terminal, a first power terminal and a second power terminal. The first control part is connected with the first control terminal of the switching element. The second control part is connected with the second control terminal of the switching element. A projection area of the first control part on a reference plane intersects with a projection area of the second control part on the reference plane at one or more first intersections. The first power part is connected with the first power terminal of the switching element. The second power part is connected with the second power terminal of the switching element.

A switching module includes a substrate, a switching element, a first control part, a second control part, a first power part and a second power part. The switching element is disposed on the substrate. The switching element includes a first control terminal, a second control terminal, a first power terminal and a second power terminal. The first control part is connected with the first control terminal of the switching element. The second control part is connected with the second control terminal of the switching element. A projection area of the first control part on a reference plane intersects with a projection area of the second control part on the reference plane at one or more first intersections. The first power part is connected with the first power terminal of the switching element. The second power part is connected with the second power terminal of the switching element.