A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.

An exemplary printable composition of a liquid or gel suspension of diodes generally includes a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary apparatus may include: a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

An exemplary printable composition of a liquid or gel suspension of diodes generally includes a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary apparatus may include: a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

A baseplate for a semiconductor module comprises at least one elevation. The at least one elevation is formed integrally with the baseplate. The baseplate has a uniform first thickness or a thickness which decreases continuously from the edge regions toward the center and which is increased locally up to a maximum second thickness in the region of each of the at least one elevation.

A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.

An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.

An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.

A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

A switch circuit package module includes at least a semiconductor switch unit and at least a first capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element and the second semiconductor switch element include a plurality of sub micro-switch elements. The capacitor unit includes a plurality of capacitors configured to cooperate with the sub micro-switch elements. The capacitors are arranged in a symmetrical distribution surrounded the semiconductor switch unit, such that impedances of any two symmetrical commutation loops each of which mainly consists of one capacitor and two sub micro-switch elements from the first semiconductor switch element and second semiconductor switch element respectively are close to or the same with each other.

A switch circuit package module includes at least a semiconductor switch unit and at least a first capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element and the second semiconductor switch element include a plurality of sub micro-switch elements. The capacitor unit includes a plurality of capacitors configured to cooperate with the sub micro-switch elements. The capacitors are arranged in a symmetrical distribution surrounded the semiconductor switch unit, such that impedances of any two symmetrical commutation loops each of which mainly consists of one capacitor and two sub micro-switch elements from the first semiconductor switch element and second semiconductor switch element respectively are close to or the same with each other.