A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.

Embodiments of the present disclosure provide a technique advantageous to an improvement in performance of a semiconductor device. The semiconductor device includes a first monocrystalline semiconductor layer on which a first semiconductor element is arranged, a second monocrystalline semiconductor layer on which a second semiconductor element is arranged, and a thin film transistor electrically connected to the first semiconductor element without an intervention of another semiconductor element arranged on the first monocrystalline semiconductor layer and electrically connected to the second semiconductor element without an intervention of another semiconductor element arranged on the second monocrystalline semiconductor layer.

A method includes forming a fin structure over a semiconductor substrate; forming a liner covering the fin structure; etching back the liner to expose an upper portion of the fin structure; forming a spacer covering the upper portion of the fin structure; etching the liner to expose a middle portion of the fin structure, wherein the remaining liner covers a lower portion of the fin structure; etching the middle portion of the fin structure; and forming a first source/drain structure surrounding the middle portion of the fin structure.

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.

In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises at least two power transistors, an input node on a first side of the respective semiconductor die, a reference node on the first side of the respective semiconductor die, and a switch node on a second side of the respective semiconductor die. The device further comprises a first conductive element electrically connected to the respective input nodes of the at least two semiconductor die. The device further comprises a second conductive element electrically connected to the respective reference nodes of the at least two semiconductor die.

A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

An integrated circuit may include oscillator circuitry having a resonator formed from fin field-effect transistor (FinFET) devices. The resonator may include drive cells of alternating polarities and sense cells interposed between the drive cells. The resonator may be connected in a feedback loop within the oscillator circuitry. The oscillator circuitry may include an amplifier having an input coupled to the sense cells and an output coupled to the drive cells. The oscillator circuitry may also include a separate inductor and capacitor based oscillator, where the resonator serves as a separate output filter stage for the inductor and capacitor based oscillator.