An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

An electronic device is provided in the present disclosure. The electronic device includes a substrate and a light emitting diode. The light emitting diode is bonded to the substrate through a solder alloy. The solder alloy includes tin and a metal element M, and the metal element M is one of the indium and bismuth. The atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.

A display device has a display region and a side region adjacent to the display region and includes a plurality of display units, a plurality of sensing units, a display driver and a sensor driver. The plurality of display units and the plurality of sensing units are disposed in the display region. The display driver is coupled to at least a portion of the plurality of display units, and includes a plurality of first thin-film transistors having a first channel layer. The sensor driver is coupled to at least a portion of the plurality of sensing units, and includes a plurality of second thin-film transistors having a second channel layer. At least a portion of the plurality of first thin-film transistors and at least a portion of the plurality of second thin-film transistors are disposed in the side region.

A display according to various embodiments may include: a first face oriented in a first direction; a second face oriented in a second direction opposite the first direction; a plurality of pixels disposed in a space between the first face and the second face; and a plurality of pins disposed on the second face and configured to electrically connect the plurality of pixels to an external device. Each of the plurality of pixels may include a plurality of LEDs and a driving circuit. A conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit may be located in the space and a wiring line configured to electrically connect the driving circuit to the plurality of pins may be located in the space.

Disclosed in the present invention are a method for manufacturing a thin-film transistor, an array substrate, and a display device. The method includes: forming a buffer layer on a substrate; forming a polysilicon layer on the buffer layer; performing a patterning process on the polysilicon layer, to form an active layer; depositing a gate insulating layer on the active layer; depositing a gate metal layer on the gate insulating layer, and performing dry etching on the gate metal layer by using the patterning process and by using a gas containing CO as an etching gas, to form a gate; performing ion implantation on the active layer by using the gate as a mask, to form a source region and a drain region; and depositing a passivation layer on the gate, forming through holes in the gate insulating layer and the passivation layer, and manufacturing a source and a drain.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A light-emitting diode (LED) projector includes an LED display panel and a projection lens arranged in front of LED display panel and configured to collect and project light emitted by the LED display panel. The LED display panel includes an LED panel and a micro lens array arranged over the LED panel. The LED panel includes a substrate, a driver circuit array on the substrate and including a plurality of pixel driver circuits arranged in an array, and an LED array including a plurality of LED dies each being coupled to one of the pixel driver circuits. The micro lens array includes a plurality of micro lenses each corresponding to and being arranged over at least one of the LED dies.

A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA ITT includes at least one three-dimensional (3D) semiconductor slab with a channel region and a first surface. A first gate structure surrounds the channel region in the first GAA FET, and a second gate structure surrounds the channel region in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some examples, a first crystal structure of the 3D semiconductor slab in the first GAA FET has a first orientation, and a second crystal structure of the 3D semiconductor slab in the second GAA FET has a different orientation for improved carrier mobility.

A display apparatus includes a display panel, a driving integrated circuit (IC), and an anisotropic conductive film. The display panel includes a non-display area adjacent to a display area and an upper substrate and a lower substrate. The driving IC overlaps the non-display area. The anisotropic conductive film attaches the driving IC to the lower substrate and includes conductive balls with diameters that gradually increase toward the display area.

Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.