A display apparatus, including a circuit substrate, a driving unit and a light-emitting unit is provided. The driving unit is disposed on the circuit substrate. The light-emitting unit is disposed on the circuit substrate. A thickness of the driving unit is substantially the same as a thickness of the light-emitting unit.

A display apparatus includes a display panel, a driving integrated circuit (IC), and an anisotropic conductive film. The display panel includes a non-display area adjacent to a display area and an upper substrate and a lower substrate. The driving IC overlaps the non-display area. The anisotropic conductive film attaches the driving IC to the lower substrate and includes conductive balls with diameters that gradually increase toward the display area.

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a harrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

A display device includes a substrate, at least one light emitting unit bound on the substrate, a transparency controllable unit disposed on the substrate, and an integrated circuit unit overlapped with the substrate. The integrated circuit unit includes a semiconducting structure and a conductive structure overlapped with the semiconducting structure. The integrated circuit unit is electrically connected to the at least one light emitting unit and the transparency controllable unit.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A display according to various embodiments of the present disclosure may include: a first face oriented in a first direction; a second face oriented in a second direction opposite the first direction; a plurality of pixels disposed in a space between the first face and the second face; and a plurality of pins disposed on the second face and configured to electrically connect the plurality of pixels to an external device. Each of the plurality of pixels may include a plurality of LEDs and a driving circuit, the plurality of LEDs may be disposed in the space such that light-emitting portions thereof face the first face, a conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit may be located in the space, at least a portion of the conductive pattern being located above the plurality of LEDs when viewed from above the second face, and a wiring line configured to electrically connect the driving circuit to the plurality of pins may be located in the space, the wiring line being located above the plurality of LEDs when viewed from above the second face.

It is an object of the present invention to provide a semiconductor device in which a sophisticated integrated circuit using a polycrystalline semiconductor is formed over a substrate which is weak with heat such as a plastic substrate or a plastic film substrate and a semiconductor device which transmits/receives power or a signal without wires, and a communication system thereof. One feature of the invention is that a semiconductor device, specifically, a processor, in which a sophisticated integrated circuit is fixed to a plastic substrate which is weak with heat by a stripping method such as a stress peel of process method to transmit/receive power or a signal without wires, for example, with an antenna or a light receiving element.

An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes: a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate; a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes. The array substrate further includes: a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer and the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT.

An electronic device and a manufacturing method thereof are disclosed. The manufacturing method of an electronic device includes following steps: forming a flexible substrate on a rigid carrier plate; forming at least a thin-film device on the flexible substrate; forming a conductive line on the flexible substrate, wherein the conductive line is electrically connected with the thin-film device; forming at least an electrical connection pad on the flexible substrate, wherein the electrical connection pad is electrically connected with the conductive line, and the thickness of the electrical connection pad is between 2 and 20 microns; disposing at least a surface-mount device (SMD) on the flexible substrate, wherein the SMD is electrically connected with the thin-film device through the electrical connection pad and the conductive line; and removing the rigid carrier plate.