An electronic component includes a first set comprising an interconnect layer and an electronic circuit having a front face and a back face, which is connected to the interconnect layer by the front face, wherein the first set comprises a metal plate having a front face and a back face joined to the back face of the electronic circuit; a coupling agent between the front face of the metal plate and the back face of the electronic circuit, configured to thermally and electrically connect the metal plate to the electronic circuit; and in that the electronic component comprises: one or more layers made of organic materials stacked around the first set and the metal plate using a printed circuit-type technique and encapsulating the electronic circuit; a thermally conductive metal surface arranged at least partially in contact with the back face of the metal plate.

A high frequency module includes a power amplifier and a substrate on which the power amplifier is mounted. The power amplifier includes a first external terminal and a second external terminal formed on a mounting surface. The substrate includes a first land electrode and a second land electrode formed on one principal surface. The first external terminal is connected to the first land electrode, and the second external terminal is connected to the second land electrode. A distance from the mounting surface to a connection surface of the first external terminal is shorter than a distance from the mounting surface to a connection surface of the second external terminal, and a distance from a connection surface of the first land electrode to the one principal surface is longer than a distance from a connection surface of the second land electrode to the one principal surface.

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Embodiments for a packaged semiconductor device and methods of making are provided herein, where a packaged semiconductor device includes a package body having a recess in which a pressure sensor is exposed; a polymeric gel within the recess that vertically and laterally surrounds the pressure sensor; and a protection layer including a plurality of beads embedded within a top region of the polymeric gel.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.

A semiconductor device includes: a multilayer wiring substrate including a plurality of wiring layers; a first semiconductor chip disposed on the wiring substrate; and a bonding layer bonding the first semiconductor chip to the wiring substrate. A trace formed on the wiring substrate includes a first trace width portion and a second trace width portion, a width of the first trace width portion being greater than the second trace width portion.

A package comprising a first integrated device comprising a first plurality of under bump metallization interconnects; a second integrated device comprising a second plurality of under bump metallization interconnects; a bridge coupled to the first integrated device and the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge; a metallization portion located over the first integrated device, the second integrated device, the bridge and the encapsulation layer, where the metallization portion includes at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects, the first plurality of interconnects located in the encapsulation layer; and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects, the second plurality of pillar interconnects located in the encapsulation layer.

A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer. A modified access region is provided at an upper surface of the barrier layer opposite the channel layer. The modified access region includes a material having a lower surface barrier height than the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between source contact and the drain contact.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.