A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 μm/1.5 μm. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.

Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

A semiconductor package includes; a package substrate, a semiconductor chip on the package substrate, an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, and a sealing member contacting the semiconductor chip and the electromagnetic shield structure, wherein the side cover includes first through holes and the upper cover includes second through holes.

A package that includes a substrate, an integrated device, a first encapsulation layer and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

A semiconductor package including a semiconductor chip, and a package structure configured to accommodate the semiconductor chip, and a manufacturing method thereof are disclosed. The package structure includes a substrate having one surface and the other surface opposite to the one surface, at least one conductive via extending through one surface and the other surface of the substrate, a wiring layer formed at one surface of the substrate, to transmit an electrical signal, a chip accommodating portion formed through removal of a portion of the substrate from the other surface toward the one surface, and a contact pad connected to the wiring layer and formed to be exposed through the chip accommodating portion. The semiconductor chip is inserted into the chip accommodating portion and is connected to the contact pad. Since the semiconductor chip is mounted after formation of the package structure, yield of the semiconductor package increases.

A high-frequency package includes a radio wave shielding portion that shields radio waves radiated from a high-frequency component, a radio wave absorber that is arranged facing the high-frequency component and that absorbs the radio waves, and an adjusting means that enables adjustment of distance from the radio wave absorber to the high-frequency component by adjusting a position of the radio wave absorber with respect to the radio wave shielding portion.

Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.