A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.

The semiconductor device includes a substrate having a main surface, a plurality of conductive patterns provided on the main surface, a plurality of switching elements disposed on one of the conductive patterns, each switching element having a first electrode and a second electrode and being connected to the one of the conductive patterns through its first or second electrode, and at least one first wiring member each directly connecting the first electrodes of two switching elements that are respectively disposed on different conductive patterns and are electrically connected in parallel.

The present invention relates to a three-dimensional integrated package device for a high-voltage silicon carbide power module, comprising a source substrate, first chip submodules, a first driving terminal, a first driving substrate, a ceramic housing, a metal substrate, a water inlet, a water outlet, second chip submodules, a second driving terminal, a second driving substrate and a drain substrate from top to bottom; and each first chip submodule is composed of a driving connection substrate, a power source metal block, a first driving gate metal post, second driving gate metal posts, a silicon carbide bare chip, an insulation structure and the like. A three-dimensional integrated half-bridge structure is adopted to greatly reduce corresponding parasitic parameters.

A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

Disclosed herein are peripheral inductors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, an IC device may include a die having an inductor extending around at least a portion of a periphery of the die.

A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.

An electronic module has a rear surface-exposed conductor 10, 20, 30 having a rear surface-exposed part 12, 22, 32 whose rear surface is exposed; an electronic element 15, 25 provided on a front surface of the rear surface-exposed conductor 10, 20, 30; and a connector 60 configure to connect the rear surface-exposed conductor 10, 20, 30 and the electronic element 15, 25 or two rear surface-exposed conductors 10, 20, 30 each other. A groove 150 is provided on the front surface of the rear surface-exposed conductor 10, 20, 30. The sealing part 90 is provided with a press hole or a press impression 110, 120, 130 used to press the rear surface-exposed conductor 10, 20, 30. In an in-plane direction, a center portion of the press hole or the press impression 110, 120, 130 is provided on the side opposite to the connector 60 or the electronic element 15, 25 with respect to the groove 150.

An isolated power chip based on wafer level packaging, including: an RDL-based micro-transformer, where a primary coil of the RDL-based micro-transformer is connected to a direct-current power supply and configured to output a direct-current voltage input by the direct-current power supply; a transmitting chip connected to the primary coil of the RDL-based micro-transformer, and configured to receive the direct-current voltage, convert the direct-current voltage into an alternating current signal, and transmit the alternating current signal to a secondary coil of the RDL-based micro-transformer; and a receiving chip connected to the secondary coil of the RDL-based micro-transformer, and configured to convert the alternating current signal into a direct-current signal, generate a control signal for stabilizing the output voltage according to a change of a load, and encode the control signal for digital isolation. The present disclosure further provides a method of manufacturing an isolated power chip based on wafer level packaging.

A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced.

The present disclosure relates to power modules. The teachings thereof may be embodied in a power unit and/or a drive unit for driving the power unit, along with methods for producing a power module. For example, a power module may include: a power unit including a heat sink; a power device disposed on the heat sink; an insulating layer covering the heat sink and the power device; and a drive unit for driving the power unit, the drive unit comprising a contact element corresponding to the contact area of the power unit. An underside of the power unit is defined by an underside of the heat sink. A top side of the power unit is defined by a contact area thermally and/or electrically coupled to the power device and a surface of the insulating layer surrounding the contact area. The contact element may be disposed abutting the contact area of the power unit for making electrical and/or thermal contact with the power device.