A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver, the second optical transceiver, and the third optical transceiver are stacked in sequential order. The first optical transceiver and the third optical transceiver respectively at least one optical input/output portion for transmitting and receiving an optical signal. The plasmonic waveguide includes a first segment, a second segment, and a third segment optically coupled to one another. The first segment is embedded in the first optical transceiver. The second segment extends through the second optical transceiver. The third segment is embedded in the third optical transceiver. The first segment is optically coupled to the at least one optical input/output portion of the first optical transceiver and the third segment is optically coupled to the at least one optical input/output portion of the third optical transceiver.

To protect memory cards, such as SD type cards, and similar devices from Electrostatic Discharge (ESD), the input pads of the device include points along their edges that are aligned with correspond points on a conductive frame structure mounted adjacent the input pad to form a spark gap. The input pads are connected to a memory controller or other ASIC over signal lines that include a diode located between the input pad and the ASIC and a resistance located between the input pad and the diode. The resistance and diode are selected such that an ESD event at an input pad triggers a discharge across the spark gap before it is transmitted on to the ASIC, while also allowing a high data rate for signals along the signal line.

The objective of the invention is to provide a semiconductor module allowing the bandwidth between an MPU and a DRAM to be improved. This semiconductor module 1 comprises a logic chip 20, a RAM unit 40 which is a multi-layer RAM module, a spacer 60 disposed stacked over the RAM unit 40 in the layering direction thereof, an interposer 10 electrically connected to each of the logic chip 20 and the RAM unit 40, and a connection part 50 establishing a connection allowing for communication between the logic chip 20 and the RAM unit 40. The logic chip 20 and the spacer 60 are disposed to be adjacent to one another in a direction intersecting with the layering direction of the RAM unit 40, and the RAM unit 40 is placed on the interposer 10 while one end portion thereof overlaps with one end portion of the logic chip 20 in the layering direction. The connection part 50 connects the one end portion of the RAM unit 40 to the one end portion of the logic chip 20.

A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.

The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The second optical transceiver is stacked on the first optical transceiver. The third optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The third optical transceiver is stacked on the second optical transceiver. The plasmonic waveguide penetrates through the second optical transceiver and optically couples the at least one optical input/output portion of the first optical transceiver and the at least one optical input/output portion of the third optical transceiver.

The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

An electronic component includes: a plurality of first substrates that are connected in series along a coupling path; and a second substrate that is connected with one first substrate of the plurality of first substrates. The second substrate is in line with the one first substrate along a connection direction intersecting the coupling path, and the plurality of first substrates and the second substrate are configured to be foldable such that they are stacked.