A semiconductor package includes a first redistribution structure, a first semiconductor package on the first redistribution structure, the first semiconductor package including a first semiconductor chip which includes a first device layer and a first semiconductor substrate including a through electrode, a second semiconductor chip which is on the first semiconductor chip and includes a second device layer and a second semiconductor substrate, and a molding member surrounding the first semiconductor chip, a second redistribution structure on an upper surface of the molding member, and a second semiconductor package on the second redistribution structure, the second semiconductor package including a third semiconductor chip, wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction, and an upper surface of the second semiconductor chip is higher than the upper surface of the molding member.

A method for manufacturing a semiconductor device, the method including: a step of disposing an adhesive thermal insulation material on a semiconductor device; a step of performing reflow of the semiconductor device having the thermal insulation material disposed thereon; and a step of detaching the thermal insulation material from the semiconductor device.

A semiconductor package may include a substrate including a connection circuit, a redistribution structure, and a chip structure on the redistribution structure. The redistribution structure may include a rear redistribution layer electrically connected to the connection circuit, a first semiconductor chip between rear and front redistribution portions and electrically connection to a front redistribution layer of the front redistribution portion, a first molded portion covering at least a portion of the first semiconductor chip, and a first through-via passing through the first molded portion and electrically connecting the front and the rear redistribution layers. The chip structure may include a wiring portion having a wiring layer electrically connected to the front redistribution layer, second and third semiconductor chips on the wiring portion and electrically connected to the wiring layer, and a second molded portion covering at least a portion of each of the second and third semiconductor chips.

A semiconductor package includes: a redistribution layer including a plurality of redistribution patterns; a sub-semiconductor package including a sub-semiconductor package substrate and a first semiconductor chip that is on the sub-semiconductor package substrate, wherein the sub-semiconductor package substrate is on the redistribution layer and includes a plurality of first lower surface pads; and a second semiconductor chip on the redistribution layer and spaced apart from the sub-semiconductor package in a horizontal direction, wherein the second semiconductor chip includes a chip pad, wherein at least some of the plurality of redistribution patterns of the redistribution layer are overlapped with and electrically connected to the plurality of first lower surface pads of the sub-semiconductor package, respectively.

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

Magnetic random access memory (MRAM) fan-out wafer level packages with package level and chip level magnetic shielding and methods of forming these magnetic shields processed at the wafer-level are disclosed. The method includes providing a MRAM wafer prepared with a plurality of MRAM dies. The MRAM wafer is processed to form a magnetic shield layer over the front side of the MRAM wafer, and the wafer is separated into a plurality of individual dies. An individual MRAM die includes front, back and lateral surfaces and the magnetic shield layer is disposed over the front surface of the MRAM die. Magnetic shield structures are provided over the individual MRAM dies. The magnetic shield structure encapsulates and surrounds back and lateral surfaces of the MRAM die. An encapsulation layer is formed to cover the individual MRAM dies which are provided with magnetic shield structures. A redistribution layer (RDL) is formed over and lines exposed front surfaces of the encapsulated MRAM dies and the encapsulated MRAM dies are separated into individual MRAM fan-out wafer level packages.

A semiconductor package may include a circuit board, an interposer structure on the circuit board, a mold layer, and a first semiconductor chip and a second semiconductor chip spaced apart from each other in a first direction on a center region of the interposer structure and electrically connected to the interposer structure. The interposer structure may include a plurality of trenches in an edge region of the interposer structure and extending through the interposer structure. The mold layer may be in the plurality of trenches and may wrap the first and second semiconductor chips. The mold layer may include a penetrating portion in the plurality of trenches and a stack portion on the interposer structure. A bottom surface of the penetrating portion of the mold layer may be on a same plane as a bottom surface of the interposer structure.

Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.

A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.