A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.

Three-dimensional application specific integrated circuit (IC) architecture is described herein. In one aspect, an IC may include a first die including: a first semiconductor layer; a plurality of processing elements (PEs) located on the first semiconductor layer; and a first interface region of the first semiconductor layer, electrically coupled to the plurality of PEs and configured to communicate electrical signals with the plurality of PEs; a second die including: a second semiconductor layer; a plurality of IC elements located on the second semiconductor layer; and a second interface region of the second semiconductor layer, electrically coupled to the plurality of IC elements and configured to communicate electrical signals to the plurality of IC elements, where the first interface region and the second interface region are electrically coupled to each other and configured to transmit electrical signals between the plurality of PEs and the plurality of IC elements.

Provided is a semiconductor package including a printed circuit board (PCB) substrate, a silicon substrate on the PCB substrate, a plurality of through vias penetrating the silicon substrate, a plurality of pads on the silicon substrate and connected to at least some of the plurality of through vias, a semiconductor chip on the plurality of pads and electrically connected to the plurality of pads, and a plurality of connecting terminals between the semiconductor chip and the plurality of pads, wherein the plurality of pads include a first pad that includes a trench and a second pad, and wherein the plurality of connecting terminals include a first connecting terminal connected to the first pad, at least a part of the first connecting terminal being in the trench and a remaining part of the first connecting terminal being on the first pad, and a second connecting terminal connected to the second pad.

A semiconductor package may include a circuit board, an interposer structure on the circuit board, a mold layer, and a first semiconductor chip and a second semiconductor chip spaced apart from each other in a first direction on a center region of the interposer structure and electrically connected to the interposer structure. The interposer structure may include a plurality of trenches in an edge region of the interposer structure and extending through the interposer structure. The mold layer may be in the plurality of trenches and may wrap the first and second semiconductor chips. The mold layer may include a penetrating portion in the plurality of trenches and a stack portion on the interposer structure. A bottom surface of the penetrating portion of the mold layer may be on a same plane as a bottom surface of the interposer structure.

An integrated circuit device includes a first substrate having a first surface and a second surface opposite to the first surface, and including an active device therein, BEOL structure disposed on the first surface of the first substrate and configured to route signals, a second substrate disposed on the first surface of the first substrate with the first BEOL structure disposed therebetween, and including a passive device therein, a power distribution structure disposed on the second surface of the first substrate, a first bonding structure positioned on the first BEOL structure, and a second bonding structure disposed between the first bonding structure and the second substrate.

An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.

An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.