A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

Wireless modules having a semiconductor package attached to an antenna package and cap package are disclosed. The semiconductor package may have one or more electronic components disposed thereon. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The cap package may also be attached to the semiconductor package on a side opposing the side on which the antenna package is disposed. The cap package may provide routing and/or additional antenna elements. The cap package may also allow for thermal grease to be dispensed therethrough. The antenna package, the cap package, and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.

A semiconductor package includes a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a via penetrating through the first insulating layer and electrically connecting the connection pads to the wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the wiring pattern; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip.

A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.

A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

A semiconductor structure includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

A semiconductor package includes a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a via penetrating through the first insulating layer and electrically connecting the connection pads to the wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the wiring pattern; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip.

Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a packaged radio frequency module includes a package substrate and a semiconductor die attached to the packaged substrate. The semiconductor die includes a power supply pad, a fuse, a fuse programming transistor having a source electrically connected to the power supply pad and a gate configured to receive a fuse programming signal, a cascode transistor electrically connected between a drain of the fuse programming transistor and the fuse, and a fuse protection capacitor electrically connected between the power supply pad and a gate of the cascode transistor and operable to inhibit unintended programming of the fuse.