A printed circuit board includes an insulating material with a bump pad buried in one surface, an adhesive layer stacked on the one surface of the insulating material, an insulating layer stacked on the adhesive layer, and a cavity passing through both of the adhesive layer and the insulating layer to expose the bump pad, wherein the cavity has a cross-sectional area decreasing in a direction toward the insulating material.

A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.

A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate to permit electroplating. In addition, the method may be used to directly connect a semiconductor die to the metal substrate of the package.

A board having an electronic component embedded therein, includes a core layer having a groove with a bottom surface, an electronic component disposed above the bottom surface of the groove and spaced apart from the bottom surface of the groove, and an insulating layer disposed on the core layer and covering at least a portion of the electronic component. The insulating layer is disposed in at least a portion of a space between the bottom surface of the groove and the electronic component.

An electronic component embedded substrate includes a core layer having a first cavity and a second cavity on a first surface and a second surface of the core layer, respectively, the second surface opposite to the first surface in a thickness direction of the core layer; an electronic component disposed in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer disposed on the first insulating material and connected to the electronic component; a built-in block disposed in the second cavity; and a second insulating material covering at least a portion of the built-in block.

Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.

A photoelectric sensing integrated system and packaging method, a lens module, and an electronic device are provided. The packaging method includes: forming at least one photosensitive component, where a photosensitive component includes a photoelectric sensing chip and a light-transmitting cover plate oppositely disposed with the photoelectric sensing chip; providing a carrier substrate; bonding a CMOS peripheral chip, a capacitor and an interconnection pillar on the carrier substrate; forming an encapsulation layer on the carrier substrate, where the encapsulation layer at least fully fills space between the CMOS peripheral chip, the capacitor, and the interconnection pillar, and has at least one photoelectric sensing through-hole formed therein; placing at least the light-transmitting cover plate of the photosensitive component in a corresponding photoelectric sensing through-hole; and forming an interconnection structure to provide an electrical connection between the photoelectric sensing chip and each of the CMOS peripheral chip, the capacitor and the interconnection pillar.

A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges (802) of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate (102) to permit electroplating. In addition, the method may be used to directly connect a semiconductor die (202) to the metal substrate (102) of the package.

Disclosed are a micro LED group substrate provided with a plurality of micro LEDs, a method of manufacturing the same, a micro LED display panel, and a method of manufacturing the same. More particularly, disclosed are a micro LED group substrate provided with a plurality of micro LEDs, a method of manufacturing the same, a micro LED display panel, and a method of manufacturing the same, wherein the need for a micro LED replacement process is eliminated.