A method for forming a package structure is provided. The method includes etching a top surface of a substrate to form a cavity. The substrate includes thermal vias directly under a bottom surface of the cavity. The method also includes forming at least one first electronic device in the cavity of the substrate. The first electronic device is thermally coupled to the thermal vias. The method further includes forming an encapsulating material in the cavity, so that the encapsulating material extends along sidewalls of the first electronic device and covers a surface of the first electronic device opposite the bottom surface of the cavity. In Addition, the method includes forming an insulating layer having an RDL structure over the encapsulating material. The RDL structure is electrically connected to the first electronic device.

Disclosed are a laser bonding apparatus and a laser bonding method capable of bonding an electronic component to a three-dimensional structure having a regular or irregular shape in a curved portion such as an automobile tail lamp or a headlamp. The laser bonding apparatus and method for a three-dimensional structure may prevent misalignment and poor bonding of the electronic component with respect to the three-dimensional structure.

Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

An electronic package device and a carrier structure thereof are provided. The carrier structure includes a die attach paddle, a ground frame, a pin assembly, and a ground wing portion. The ground frame surrounds the die attach paddle. The pin assembly includes a plurality of pins that are spaced apart from one another. The pins extend radially outward and are arranged to surround the ground frame. The ground wing portion is connected to the ground frame and located in a space under the pin assembly. The ground wing portion includes an extending part and a joint part, the extending part extends away from the die attach paddle, and a top end of the extending part is located at a position above where a bottom surface of the die attach paddle is located.

A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section view, and a distance from the first position to the first out contour is greater than that from the second position to the first outer contour.

The vibrator device includes: a base; a circuit element disposed on the base; a vibrating element disposed to at least partially overlap the circuit element in a plan view; and a support substrate that is disposed between the circuit element and the vibrating element and supports the vibrating element. In addition, the vibrating element has a frequency adjustment portion that performs frequency adjustment by removing at least a part of the vibrating element, and the support substrate includes a base portion that supports the vibrating element, a support portion that supports the base portion, a beam portion that couples the base portion the support portion, and a shielding portion that is connected to the beam portion, overlaps the frequency adjustment portion in a plan view, and has light shielding properties.