Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

A semiconductor package includes a semiconductor device on a first redistribution substrate and having a first sidewall, and a mold layer that covers the semiconductor device and the first redistribution substrate. The first redistribution substrate includes a first redistribution dielectric layer, a first reinforcement pattern on the first redistribution dielectric layer and overlapping the semiconductor device and the mold layer, and first and second bonding pads that penetrate the first redistribution dielectric layer and contact the first reinforcement pattern. The second bonding pad is spaced apart from the first bonding pad in a first direction. The first bonding pad has a first width in a second direction orthogonal to the first direction. When viewed in a plan view, the first reinforcement pattern has a second width in the second direction below the first sidewall. The second width is greater than the first width.

A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof.

A semiconductor package includes a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A connector is disposed on the second side.

A semiconductor device has a substrate and plurality of first bumps formed over the substrate in an array. An array of second bumps is formed over the substrate on at least two sides of the first bumps. An electrical component is disposed over the first bumps. A package structure is disposed over the substrate and electrical component. The package structure has a horizontal member and legs extending from the horizontal member to form a cavity. The package structure is coupled to the array of second bumps. The package structure includes a material to operate as a heat sink or shielding layer. The shielding layer makes ground connection through the array of second bumps. The first bumps and second bumps have a similar height and width to form in the same manufacturing step. A protective layer, such as conductive epoxy, is disposed over the array of second bumps.

A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.