A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

A semiconductor device includes: a substrate; a semiconductor element disposed on the substrate; a plurality of electrodes disposed on the substrate separately from one another and arranged so as to surround the semiconductor element in a plan view; a lid that cover the semiconductor element, the lid including an inner portion and a periphery portion that is outer than the inner portion in a plan view, the lid including a plurality of first protruding members that is provided separately from one another, the first protruding members being disposed in the inner portion; and conductive members disposed between the plurality of electrodes and the plurality of protruding members disposed in positions opposed to the plurality of electrodes respectively, the conductive members being joined to the plurality of electrodes and the plurality of protruding members respectively.

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by forming through openings that extend through a metallic carrier between first and second surfaces of the metallic carrier, attaching a chip-on-interposer subassembly on the metallic carrier using an adhesive, with the chip inserted into a cavity of the metallic carrier, and with the chip-on-interposer subassembly attached to the metallic carrier, forming first and second buildup circuitry on a first surface of the interposer and the second surface of the metallic carrier, respectively, and subsequently forming plated through holes that extend into the through openings to provide electrical and thermal connections between the first and second buildup circuitry. The method and resulting device advantageously provides vertical signal routing and stacking capability for a semiconductor package.

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

A disclosed semiconductor structure may include an interposer, a first semiconductor die electrically coupled to the interposer, a packaging substrate electrically coupled to the interposer, and a capping layer covering one or more of a first surface of the first semiconductor die and a second surface of the packaging substrate. The capping layer may be formed over respective surfaces of each of the first semiconductor die and the packaging substrate. In certain embodiments, the capping layer may be formed only on the first surface of the first semiconductor die and not formed over the package substrate. In further embodiments, the semiconductor structure may include a second semiconductor die, such that the capping layer covers a surface of only one of the first semiconductor die and the second semiconductor die. The semiconductor structure may include a molding compound die frame that is partially or completely covered by the capping layer.

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.