In an embodiment, a semiconductor device includes: a mounting substrate having electrically conductive formations thereon, a semiconductor die coupled with the mounting substrate, the semiconductor die with electrical contact pillars facing towards the mounting substrate, an anisotropic conductive membrane between the semiconductor die and the mounting substrate, the membrane compressed between the electrical contact pillars and the mounting substrate to provide electrical contact between the electrical contact pillars of the semiconductor die and the electrically conductive formations on the mounting substrate.

In an embodiment, a semiconductor device includes: a mounting substrate having electrically conductive formations thereon, a semiconductor die coupled with the mounting substrate, the semiconductor die with electrical contact pillars facing towards the mounting substrate, an anisotropic conductive membrane between the semiconductor die and the mounting substrate, the membrane compressed between the electrical contact pillars and the mounting substrate to provide electrical contact between the electrical contact pillars of the semiconductor die and the electrically conductive formations on the mounting substrate.

The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by forming through openings that extend through a metallic carrier between first and second surfaces of the metallic carrier, attaching a chip-on-interposer subassembly on the metallic carrier using an adhesive, with the chip inserted into a cavity of the metallic carrier, and with the chip-on-interposer subassembly attached to the metallic carrier, forming first and second buildup circuitry on a first surface of the interposer and the second surface of the metallic carrier, respectively, and subsequently forming plated through holes that extend into the through openings to provide electrical and thermal connections between the first and second buildup circuitry. The method and resulting device advantageously provides vertical signal routing and stacking capability for a semiconductor package.

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

A chip package structure is provided. The chip package structure includes a semiconductor die formed over a package substrate and an interconnect structure bonded and electrically connected between the semiconductor die and the package substrate. The chip package structure also includes a stiffener structure formed over the package substrate and covering the semiconductor die. The metal stiffener structure has a metal lid cap portion covering the upper surface of the semiconductor die, a metal ring portion surrounding the metal lid cap portion, and a metal spacer wall portion extending between the metal ring portion and the package substrate to surround the semiconductor die.

The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface. The heat spreader also includes a first copper portion covering the first major surface of the graphene grid, a second copper portion covering the second major surface of the graphene grid, and a plurality of copper vias filling the plurality of holes.

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

A disclosed semiconductor device includes a package substrate, a first semiconductor die coupled to the package substrate, a package lid attached to the package substrate and covering the semiconductor die, and a thermal interface material located between a top surface of the semiconductor die and an internal surface of the package lid. The semiconductor device may further include a dam formed on the internal surface of the package lid. The dam may constrain the thermal interface material on one or more sides of the first semiconductor die such that the thermal interface material is located within a predetermined volume between the top surface of the first semiconductor die and the internal surface of the package lid during a reflow operation. The package lid may include a metallic material and the dam may include an epoxy material formed as a single continuous structure or may be formed as several disconnected structures.