H01L2924/17747

SEMICONDUCTOR DEVICE WITH ISLAND AND ASSOCIATED LEADS
20190385937 · 2019-12-19 ·

A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

ELECTRONIC DEVICE WITH MULTI-LAYER CONTACT AND SYSTEM

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Semiconductor device

A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.

Bottom package exposed die MEMS pressure sensor integrated circuit package design

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.

Method for producing electronic device with multi-layer contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.

Semiconductor device with island and associated leads
10431527 · 2019-10-01 · ·

A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

Integrated circuit package for assembling various dice in a single IC package

An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate.

Method of manufacturing a semiconductor device
10403616 · 2019-09-03 · ·

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole.

Method Of Making A Wire Support Leadframe For A Semiconductor Device
20190172776 · 2019-06-06 ·

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

LEADLESS SEMICONDUCTOR PACKAGES, LEADFRAMES THEREFOR, AND METHODS OF MAKING

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.