Methods and apparatus to provide clutter rejecting built-in-test and/or fault isolation of individual array elements in assignment-based AESAs. BIT beam states for array element testing can be stored in AESA memory for rapid assignment sequencing of RF waveform generators and receive processing. Simultaneously transmitted signals for BIT sequences have unique signal characteristics that allow test signal clutter rejection on the receive side processing.

A phased array antenna system includes a plurality of radio frequency (RF) tile sub-arrays. Each RF tile sub-array includes a multiplicity of RF elements, a tile control integrated circuit, a multiplicity of RF integrated circuits and a configuration storage device. The configuration storage device stores data including calibration and configuration information that is unique to the RF tile sub-array and the tile control integrated circuit. The multiplicity of RF integrated circuits, the multiplicity of RF elements, and the configuration storage device are disposed on a single associated RF tile sub-array. The system also includes an antenna controller configured to process data for steering or tracking one or more RF beams by the multiplicity of RF elements. The calibration and configuration information that is unique to the RF tile sub-array is downloaded from the configuration storage device through the tile control integrated circuit to an RF element compensation table.

A liquid crystal panel included in a scanning antenna includes: a TFT substrate including a first dielectric substrate, a TFT supported on the first dielectric substrate, a gate bus line, a source bus line, a patch electrode, and a first alignment film covering the patch electrode; a slot substrate including a second dielectric substrate, a slot electrode formed on a first main surface of the second dielectric substrate and including a slot arranged corresponding to the patch electrode, and a second alignment film covering the slot electrode; and a liquid crystal layer provided between the TFT substrate and the slot substrate and containing a liquid crystal molecule having an isothiocyanate group. The patch electrodes and the slot electrode are each formed of a Cu layer or an Al layer, and the first alignment film and the second alignment film each include a compound having an atomic group forming a coordinate bond with Cu or Al.

This TFT substrate includes a TFT provided with a gate electrode, a source electrode, and a drain electrode; a gate metal layer including the gate electrode; a gate insulating layer formed on the gate metal layer; and a source metal layer that is formed on the gate insulating layer and includes the source electrode, the drain electrode, and a patch electrode. The source metal layer includes a first metal layer that contains one of Ti, Mo, Ta, W and Nb, and a second metal layer that is formed on the first metal layer and contains one of Cu, Al, Ag and Au. The source electrode and the drain electrode each include the first metal layer and the second metal layer. A distance from the first metal layer of the source electrode to the first metal layer of the drain electrode in a channel direction is less than a distance from the second metal layer of the source electrode to the second metal layer of the drain electrode in the channel direction.

A phased array antenna system includes a plurality of radio frequency (RF) tile sub-arrays. Each RF tile sub-array includes a multiplicity of RF elements, a tile control integrated circuit, a multiplicity of RF integrated circuits and a configuration storage device. The configuration storage device stores data including calibration and configuration information that is unique to the RF tile sub-array and the tile control integrated circuit. The multiplicity of RF integrated circuits, the multiplicity of RF elements, and the configuration storage device are disposed on a single associated RF tile sub-array. The system also includes an antenna controller configured to process data for steering or tracking one or more RF beams by the multiplicity of RF elements. The calibration and configuration information that is unique to the RF tile sub-array is downloaded from the configuration storage device through the tile control integrated circuit to an RF element compensation table.

A broadband phased array antenna system is set forth comprising a support member; an antenna array mounted to the support member, the antenna array having a plurality of uniformly excited hybrid radiating elements arranged in a symmetric array on a substrate; a baseband controller mounted to the support member; a radio controller mounted to the support member for modulating and demodulating signals between the baseband controller and antenna array; and a communications interface for removably connecting and disconnecting the antenna system. In one aspect, the antenna array comprises a substrate; a plurality of uniformly excited hybrid radiating elements arranged in a symmetric array on the substrate; a hybrid feeding network for transmitting RF-signals to the hybrid radiating elements; and artificial materials surrounding opposite sides of the symmetric array for suppressing edge scattered fields and increasing gain of the antenna system.

A system includes a phased array antenna that is used to emulate antennas that have larger solid angle coverage and lower gain compared to a single beam of the phased array antenna. This is achieved by switching between beams of the phased array antenna while receiving a wireless communication signal and summing representations of signal energy received using the different beams. The system can be used to narrow down the angular coordinates of a transmitting satellite by emulating antenna patterns that cover portions of a search space. The system can also be used to determine a channel discriminator (e.g., frequency, code, time slot) that defines a signal being transmitted.

A mode S Interrogation Side Lobe Suppression System (ISLS) for an electronically scanned interrogator is described. One aspect introduces the 90 phase offset between the main and control beams thereby enabling the full power capability of the TRU to be effectively utilized and the effective beamwidth in Mode S to be sharply defined. The system allows the transmission of the simultaneous ISLS pulse of a Mode S all-call interrogation to be transmitted using the same array as is used by the main beam.

An active phased array antenna system with hierarchical modularized architecture is introduced, which includes an array antenna and a beamforming circuit. The array antenna includes a plurality of antenna units, number of which is N and which are arranged in array form. The beamforming circuit is for receiving a plurality of input signals and a plurality of phase control signals, and includes a hierarchical circuit structure based on phase shifters, for outputting a plurality of output signals based on the input signals according to phase values corresponding to the phase control signals and combinations of the phase values; the output signals are respectively coupled to the antenna units so as to generate a radiation pattern, wherein number of the phase control signals is T, T<N, wherein N=.sub.i=1.sup.PN.sub.i, M=.sub.i=1.sup.PN.sub.i, MPTM, N.sub.i (i=1 to P), M, P are all positive integers, P2, N.sub.i2.

An active phased array antenna system with hierarchical modularized architecture is introduced, which includes an array antenna and a beamforming circuit. The array antenna includes a plurality of antenna units, number of which is N and which are arranged in array form. The beamforming circuit is for receiving a plurality of input signals and a plurality of phase control signals, and includes a hierarchical circuit structure based on phase shifters, for outputting a plurality of output signals based on the input signals according to phase values corresponding to the phase control signals and combinations of the phase values; the output signals are respectively coupled to the antenna units so as to generate a radiation pattern, wherein number of the phase control signals is T, T<N, wherein N=.sub.i=1.sup.PN.sub.i, M=.sub.i=1.sup.PN.sub.i, MPTM, N.sub.i (i=1 to P), M, P are all positive integers, P2, N.sub.i2.