Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

A hybrid power converter circuit includes a switched-capacitor power converter stage and a pulse-width modulation (PWM) or resonant output circuit coupled to a switching node of the switched-capacitor power converter stage. In particular, the PWM or resonant output circuit can include a transformer having a primary winding and a secondary winding magnetically coupled to each other, and the secondary winding is coupled to the output node of the power converter. The switched-capacitor power converter stage is coupled between the input node of the power converter and the primary winding of the transformer, and includes capacitors and switches configured to connect the capacitors to the input node during a first phase of operation and connect the capacitors to the primary winding of the transformer of the PWM or resonant output circuit during a second phase of operation.

A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

A cascade multiplier includes a switch network having switching elements, a phase pump, and a network of pump capacitors coupled with the phase pump and to the switch network. The network of pump capacitors includes first and second capacitors, both of which have one terminal DC coupled with the phase pump, and a third capacitor coupled with the phase pump through the first capacitor.

A charge pump unit including a capacitor that accumulates a charge on an output node according to a first clock signal and a transfer gate that takes in and applies a voltage of an input node to the output node according to a second clock signal received at a control terminal is controlled in the following manner. If the ratio of the total time of periods in which the voltage of the output node is higher than a target voltage in a predetermined monitoring period is smaller than or equal to a first threshold, i.e., if the charge pump unit executes a boosting operation for a relatively long period, a pulse voltage value of the second clock signal is increased.

There is described a rectifier circuit for providing and limiting a supply voltage to an RFID tag, the circuit including a pair of antenna input terminals configured to receive an input signal from an RFID tag antenna. A plurality of charge pump stages are coupled in cascade in such a way that an input terminal of a first charge pump stage in the cascade is connected to ground and an input terminal of each subsequent charge pump stage in the cascade is coupled to an output terminal of the preceding charge pump stage in the cascade. A control logic is configured to select the output terminal of one charge pump stage among the plurality of charge pump stages to provide the supply voltage. Furthermore, an RFID tag and a method of providing and limiting a supply voltage to an RFID tag are described.

Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.

An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.

The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.