A voltage generation system might include a selectively-enabled resistive voltage divider having a first resistor connected between an output of the voltage generation system and a first feedback node and having a second resistor connected between the first feedback node and a first voltage node; a selectively-enabled capacitive voltage divider having a first capacitor connected between the output and a second feedback node and having a second capacitor connected between the second feedback node and the first voltage node; a comparator having a first input connected to the second feedback node, having a second input connected to a control signal node, and having an output; and a voltage generation circuit configured to generate a voltage level at the output responsive to a logic level of the output of the comparator and to a clock signal; wherein the first feedback node is selectively connected to the second feedback node.

Various embodiments of a fault detector for a voltage converter are described. In one example embodiment, briefly, the fault detector is capable to detect one or more fault events during operation of a voltage converter. Likewise, the fault detector is capable to generate one or more fault signals with respect to the one or more to be detected fault events. The one or more fault signals, in the example embodiment, to signal a disconnect switch of the voltage converter to electrically disconnect or otherwise via a high impedance state to limit current flow through at least one switch of a set of switches of the voltage converter. In another example embodiment, the fault detector, responsive to the one or more fault signals, capable to generate a bus interrupt signal on a pin out, such as of an integrated circuit (IC) for use with the voltage converter, or capable to toggle a fault indicator pin out of the IC. Other additional embodiments are also described.

Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

A charge pump generates an output voltage. A first circuit generates a pulse width-modulated signal as a function of a deviation between the output voltage and a setpoint voltage. A second circuit receives a periodic signal and conditions the supply of the periodic signal to a control input of the charge pump as a function of the state of the pulse width-modulated signal.

A high voltage generating circuitry includes a charge-pump and control loop; the control loop includes a voltage divider which receives a high voltage and provides a divided high voltage output. A first circuit element provides a first voltage difference signal. A controller generates a feedback signal based on the first voltage difference signal. An oscillator generates clock signals for operating the charge-pump circuitry, with the frequency of the clock signals being controlled with a control signal. A feedforward path with a second circuit element combines a second reference voltage and a second voltage generated by inverting the supply voltage for obtaining a second voltage difference signal. A third circuit element generates a feedforward compensation signal inversely proportional to a voltage difference between the supply voltage and the second reference voltage. A fourth circuit element generates the control signal by summing the feedback signal and the feedforward compensation signal.

A gate driving circuit for a charge pump with slowed rates of current change for reduced EMI emissions includes at least one gate driving sub-circuit. Each gate driving sub-circuit includes a first current mirror, a first PMOS transistor, a first NMOS transistor, and a second current mirror. Gates of the first PMOS transistor and the first NMOS transistor receive a clock signal. Drains of the first PMOS transistor and the first NMOS transistor output a driving signal. When the first PMOS transistor is turned on, the first current mirror provides a charging current. When the first NMOS transistor is turned on, the second current mirror provides a discharge current.

A voltage converter includes a first to a third capacitor, a supply terminal, a first and a second clock terminal and a transfer arrangement, wherein a first electrode of the first capacitor is connected to the first clock terminal and a second electrode of the first capacitor is connected to a first node of the transfer arrangement, wherein a first electrode of the second capacitor is connected to the second clock terminal and a second electrode of the second capacitor is connected to a second node of the transfer arrangement, and wherein a first electrode of the third capacitor is permanently and directly connected to the second electrode of the first capacitor and a second electrode of the third capacitor is connected to a third node of the transfer arrangement.

A control method used in a switched tank converter with a first conversion unit, a second conversion unit and a rectification unit, includes: based on current flowing through the resonant tanks in the first and second conversion units, determining when to turn on the high side switches of the first and second conversion units, and when to turn on the low side switches of the first and second conversion units; detecting whether current flowing through the first, second, third and fourth rectification switches crosses zero; and based on the detection result, respectively determining when to turn off the high side switch of the first conversion unit, when to turn off the high side switch of the second conversion unit, when to turn off the low side switch of the second conversion unit, and when to turn off the low side switch of the first conversion unit.

Circuits and methods for controlling the startup of multiple parallel power converters that avoid in-rush current and/or switch over-stress in an added power converter or a power converter having one or more fault conditions. Embodiments include node status detectors coupled to selected nodes within parallel-connected power converters to monitor voltage and/or current, and configured in some embodiments to work in parallel with an output status detector measuring the output voltage of an associated power converter during startup. With charge pump-based power converters, the node status detectors ensure that the pump capacitors of each power converter are adequately charged while the output capacitor is charged as well. For such embodiments, a soft-start period of startup may be considered finished if both the shared output capacitors and the pump capacitors of each power converter are charged to selected target values. Embodiments may also be used for fault detection during steady-state operation.

A voltage generator supplies a voltage to an electronic device of a Light Detection and Ranging (LiDAR) system. The voltage generator includes a clock source configured to generate a clock signal and a voltage source configured to generate a first voltage signal having a first voltage level. The voltage generator also includes a voltage multiplier coupled to the voltage source and the clock source. The voltage multiplier is configured to generate a second voltage signal having a second voltage level based on the first voltage signal and the clock signal. The second voltage level is higher than the first voltage level.