A switched tank converter includes at least three conversion units. Each conversion unit is a first-type conversion unit or a second-type conversion unit. An end of the support capacitor of each first-type conversion unit is electrically connected with a ground end. An end of a half-bridge clamping circuit of the second-type conversion unit is electrically connected with the ground end. A middle point of the half-bridge clamping circuit is electrically connected with an end of the support capacitor of the second-type conversion unit. The first-stage conversion unit is the first-type conversion unit. At least one conversion unit of the third-stage conversion unit to the Nth-stage conversion unit is the second-type conversion unit. Another end of the half-bridge clamping circuit of at least one second-type conversion unit is electrically connected with another end of the support capacitor of the lower-stage conversion unit excluding the first-stage conversion unit.

Circuits, methods, and system for DC voltage conversion are disclosed. A charge pump circuit is described that includes input switches and output switches that are individually controlled by different clock signals to alternatively couple energy storage capacitors to an input and to an output. The individualized switching control allows for the use of clock signals with no overlapping transitions to improve conversion efficiency. Additionally, the input switches are controlled by clock signals that are level shifted relative to the input voltage. The level shifted switching control also improves efficiency and allows for a range in input voltages to be accommodated for DC voltage conversion.

A charge pump includes a first pumping capacitor configured to pump a first voltage of a first node, in response to a first clock signal, a gate pumping capacitor configured to pump a second voltage of a second node, in response to a second clock signal, a charge transfer transistor including a first source connected to a first one of a third node and the first node, a first gate connected to the second node, and a first drain connected to a remaining one of the first node and the third node, a gate control transistor including a second source connected to the first one of the third node and the first node, a second gate connected to the remaining one of the first node and the third node, and a second drain connected to the second node, and a gate discharge or charge unit.

A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide at an output terminal of the first charge pump a first charge pump voltage; a second charge pump having an input terminal coupled to the output terminal of the first charge pump for receiving the first charge pump voltage and configured to boost the received first charge pump voltage to provide at an output terminal of the second charge pump a second charge pump voltage, and a voltage drop sensing device configured to detect drops in the first charge pump voltage and to deactivate second transistors of bypass units associated to the disabled charge pump stages when a drop in the first charge pump voltage is detected.

An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.

Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to the first source/drain terminal of the second and third transistors and a gate terminal coupled to the input. The gate terminal of the first transistor is coupled to the gate terminal of the second transistor.

A method and a system for DC-to-DC conversion are provided herein. The system may include a direct current to direct current (DC-to-DC) converter which may include at least one silicon-oxide-nitride-oxide-silicon (SONOS) device operable to perform voltage multiplication. The method may include directionally altering the threshold voltage of at least one silicon-oxide-nitride-oxide-silicon (SONOS) device, including applying a positive or negative voltage to at least a gate region of said at least one SONOS device thereby forcing electrons or holes from a channel region in said SONOS device to tunnel through an oxide layer (SiO), become trapped in silicon nitride (SiN), and accumulate proximate to a source region and/or a drain region in said at least one SONOS device, said accumulated electrons or holes altering the threshold voltage of said at least one SONOS device in a direction of said source or said drain region.

A voltage converter comprises a first to a third capacitor (11-13), a supply terminal (16), a first and a second clock terminal (21, 22) and a transfer arrangement (15). A first electrode of the first capacitor (11) is connected to the first clock terminal (21) and a second electrode of the first capacitor (11) is connected to a first node (23) of the transfer arrangement (15). A first electrode of the second capacitor (12) is connected to the second clock terminal (22) and a second electrode of the second capacitor (12) is connected to a second node (24) of the transfer arrangement (15). A first electrode of the third capacitor (13) is permanently and directly connected to the second electrode of the first capacitor (11) and a second electrode of the third capacitor (13) is connected to a third node (25) of the transfer arrangement (15).

An apparatus for converting a first voltage into a second voltage includes a reconfigurable switched capacitor power converter having a selectable conversion gain. The power converter has switch elements configured to electrically interconnect capacitors to one another and/or to the first or second voltage in successive states. The switch elements are configured to interconnect at least some capacitors to one another through the switch elements. A controller causes the reconfigurable switched capacitor power converter to transition between first and second operation modes. The controller minimizes electrical transients arising from transition between modes. In the first operating mode, the power converter operates with a first conversion gain. In the second operating mode, it operates with a second conversion gain.