Patent classifications
H02M3/076
Voltage multiplier circuit
In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.
BEYOND-THE-RAILS SWITCHED-CAPACITOR FLOATING FRONT END WITH OVER-VOLTAGE PROTECTION
A system may include a switched-capacitor analog front end comprising a plurality of switches for sampling an analog physical quantity and a bootstrap generation network electrically coupled to the plurality of switches and configured to generate a bootstrap sampling clock for controlling the plurality of switches and generate a floating supply voltage for the bootstrap sampling clock based on the analog physical quantity.
VOLTAGE CONVERTING CIRCUIT AND CONTROL CIRCUIT THEREOF
A voltage converting circuit and a control circuit thereof are provided. The control circuit includes a comparator, a clock generator, and a boost circuit. The comparator compares an input voltage with an output voltage to generate a comparison signal. The clock generator generates a clock signal according to the comparison signal to enable the clock signal to have a first frequency in a first time interval and to have a second frequency in a second time interval. The first frequency is higher than the second frequency. The first time interval occurs before the second time interval. The boost circuit receives the clock signal, pulls up a control signal of a driving switch in the first time interval according to a first driving capability, and generates the control signal in the second time interval according to a second driving capability. The first driving capability is greater than the second driving capability.
Voltage regulator with flexible output voltage
A voltage regulator includes a first feedback loop and a second feedback loop. The first feedback loop includes a charge pump outputting a first output voltage, a first transistor ladder and a control circuit. The first transistor ladder divides the first output voltage to generate a first feedback voltage. The control circuit receives the first feedback voltage and controls a level of the first output voltage according to the first feedback voltage and a reference voltage. The second feedback loop includes a power transistor, a second transistor ladder and an operational amplifier. The power transistor receives the first output voltage to output a second output voltage. The second transistor ladder divides the second output voltage to generate a second feedback voltage. The operational amplifier outputs a control signal to the power transistor by receiving the second feedback voltage and a reference voltage selected from one of a plurality of levels.
CHARGE-PUMP TRACKER CIRCUITRY
Charge-pump tracker circuitry is disclosed having a first switch network configured to couple a first capacitor between a voltage input terminal and a ground terminal during a first charging phase and couple the first capacitor between the voltage input terminal and a pump output terminal during a first discharging phase. A second switch network is configured to couple the second capacitor between the voltage input terminal and the ground terminal during a second charging phase and couple the second capacitor between the voltage input terminal and the pump output terminal during a second discharging phase. A switch controller is configured to control the first switch network and the second switch network so that the first discharging phase and the second discharging phase are in unison in a parallel mode and so that the first discharging phase and the second discharging phase alternate in an interleaved mode.
Regulated high voltage reference
A variable high voltage charge-pump system includes a plurality of unregulated switching stages and a plurality of regulated switching stages arranged in a cascaded configuration. The unregulated switching stages receive unregulated voltage input signals, and the regulated switching stages receive regulated voltage input signals. An amplifier generates the regulated voltage input signals to bring the output voltage to a desired value.
Electronic device with a charge recycling mechanism
An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor to store a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use charges stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a recycling duration for discharging a recycled charge from the booster capacitor to the doubler capacitor through the connecting switch, wherein the recycling duration is after generating the stage output.
Charge pump applied to organic light-emitting diode display pane
A charge pump, applied to an OLED display panel and coupled to an output capacitor, includes a first switch to a tenth switch and a first capacitor to a third capacitor. The first switch and second switch are coupled in series between a first voltage and a second voltage lower than first voltage. The third switch is coupled to second voltage. The sixth switch is coupled to first voltage. The seventh switch is coupled to second voltage. The fourth switch, eighth switch and tenth switch are coupled to output capacitor. The first capacitor is coupled between first switch and second switch. The second capacitor is coupled between fifth switch and sixth switch. The third capacitor is coupled between seventh switch and eighth switch. The charge pump is operated in a first phase, a second-A phase, the first phase and a second-B phase in order to provide negative output voltage.
ELECTRONIC DEVICE WITH A CHARGE RECYCLING MECHANISM
An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor to store a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use charges stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a recycling duration for discharging a recycled charge from the booster capacitor to the doubler capacitor through the connecting switch, wherein the recycling duration is after generating the stage output.
Methods and apparatus for generation of voltages
Methods of operating voltage generation circuits include applying a clock signal to a first electrode of a first capacitance having a second electrode connected to a first node of a first current path, applying the clock signal to a second capacitance having a second electrode connected to a gate of a second current path connected in parallel with the first current path and with the second electrode further connected to a first end of a resistance having a second end connected to the second node, passing charge across at least one of the first current path and the second current path while the clock signal has a first logic phase, and mitigating current flow across the first current path and the second current path while the clock signal has a second logic phase opposite the first logic phase, as well as apparatus facilitating such methods.