The present disclosure relates to a structure which includes a diode-based Dickson charge pump which is configured to use an independent multi-gate device to reduce a threshold voltage of a plurality of transistor diodes during a charging and pumping phase.

A residual current (e.g. common-mode current) may be present in an isolated subsystem. The isolated subsystem may include the secondary winding of a transformer while a first subsystem may include the primary winding of the transformer. The first subsystem may also include a compensation circuit. A driver circuit may generate drive signals provided to the primary winding of the transformer and also to the compensation circuit. The compensation circuit may include a variable capacitor network (e.g. a variable capacitor diode network) that receives the drive signals and also receives a bias voltage, and generates a cancellation signal according to the drive signals and the bias voltage. The compensation circuit may provide the cancellation signal to the ground plane of the isolated subsystem through a capacitor that couples the variable capacitor diode network to the ground plane, in order to reduce or cancel the residual current present in the isolation subsystem.

The present invention provides a voltage scaling-up circuit which comprises a charge pump circuit and a multiplexer circuit. The charge pump circuit which includes at least one pumping switch, and is configured to operably periodically converts an input voltage to a pumped voltage onto a pump output node through the at least one pumping switch by charging and pumping, such that the pumped voltage has a scaling factor over the input voltage, wherein the at least one pumping switch has a bulk. The multiplexer circuit senses a predetermined voltage and the pumped voltage and selects one of the predetermined voltage and the pumped voltage which has a higher magnitude as a scaled output voltage at a scaled output node; wherein the bulk of the at least one pumping switch is biased to the scaled output voltage.

To obtain a booster circuit capable of reducing voltage stress applied to a booster cell, provided is a booster circuit including a plurality of booster cells connected in series. Each of the plurality of booster cells includes a charge transfer transistor connected between an input terminal and an output terminal, and a boost capacitor connected between the input terminal and a clock terminal. Among the plurality of booster cells, a plurality of booster cells at least in a last stage are connected in parallel so that the plurality of booster cells connected in parallel are connected to a booster cell in a previous stage of the last stage by switching the plurality of booster cells in the last stage in accordance with a boosting operation.

A circuit includes a switched capacitor circuit and a voltage generator circuit. The switched capacitor circuit includes first, second, third, and fourth switches and first and second capacitors. The first capacitor has first and second terminals, the first terminal coupled to the first switch. The second capacitor has first and second terminals, the second terminal coupled to the second switch. The third switch has a terminal coupled to the second terminals of the first and second capacitors. The fourth switch has first and second terminals, the first terminal coupled the terminal of the third switch and to the second terminals of the first and second capacitors. The voltage generator circuit has an output coupled to the second terminal of the fourth switch and is configured to provide a common mode output bias voltage at the second terminal of the fourth switch responsive to a common mode input bias voltage.

Methods and apparatus for flying capacitor balancing in multilevel converters are disclosed. Example flying capacitor balancing circuitry can include voltage difference sense and control circuitry and duty cycle timing adjustment circuitry. The voltage difference sense and control circuitry can generate a compensation control signal for the duty cycle timing adjustment circuitry.

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block. Since the back gate of the transistor is not in a floating state, a current flowing through the back channel can be controlled so as to reduce a variation in the electrical characteristics of the transistor. Further, a transistor with low off-state current is used as the transistor included in the voltage conversion block, whereby storage of the output potential is controlled.

A charge pump circuit includes a first PMOS transistor and a first NMOS transistor that are connected in series to a main charging and discharging circuit, where a grid electrode of the first PMOS transistor is controlled by an inverted signal of a first control signal. A grid electrode of the first NMOS transistor is controlled by a second control signal. The circuit further includes a second PMOS transistor that is located in a first branch circuit, where a grid electrode of the second PMOS transistor is controlled by the first control signal; and includes a second NMOS transistor that is located in a second branch circuit, where a grid electrode of the second NMOS transistor is controlled by an inverted signal of the second control signal. The embodiments resolve a problem of leakage currents.

A charge pump (CP) that operates at low input voltage with high power conversion efficiency is disclosed. A first embodiment provides a negative CP used for controlling load switches of a voltage doubler. Using a negative CP extends the operating region below ground to relieve the power delivery limitation of the CP. A second embodiment provides a low power adaptive dead-time circuit, which has several dead-time signals having different lengths of dead-times and selects one according to the input voltage level. A low input voltage detector in the adaptive dead-time circuit is used to determine which dead-time should be used. A third embodiment provides a switching body bias used for the low input voltage CP. The switching body bias uses both forward and reverse body bias applied to the CP to minimize reverse current and maximize power transfer. The first, second, and third embodiments can be used together or independently.