Patent classifications
H02M7/162
METHOD AND APPARATUS TO MITIGATE DC BUS OVER-VOLTAGES ON COMMON AC BUS SYSTEMS UTILIZING DC & AC DRIVES
A method and line interface filter apparatus to couple a drive or group of drives to a shared multiphase AC bus, including individual phase circuits having an inductor coupled between a respective bus and drive phase lines, a resistor coupled to the respective drive phase line, and a capacitor coupled between the resistor and a common connection of the capacitors of the individual phase circuits, where the capacitance of the capacitors is 5 to 15 times a per-phase equivalent capacitance of the drive or group of drives, and the resistance of the resistors is two times a damping ratio times a square root of a ratio of the filter inductance to the filter capacitance, where the damping ratio is greater than or equal to 1.0 and less than or equal to 2.0.
Thyristor control
A rectifying bridge has a thyristor coupled in series with a rectifying element between a first rectified output terminal of a rectifying bridge circuit and a second rectified output terminal of the rectifying bridge circuit. A diode is coupled in series with a DC voltage source between a gate of the thyristor and the second rectified output terminal.
Bypass thyristor device with gas expansion cavity within a contact plate
A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.
Bypass thyristor device with gas expansion cavity within a contact plate
A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.
Electric circuit structure for short circuit protection
An improved electric circuit structure for short circuit protection is applicable to examining a device under test, comprising a circuit breaking element, a thermistor, a filtering and rectifying module and a capacitor. A first end of the circuit breaking element is electrically connected to a power source. A first end of the thermistor is electrically connected to a ground. The filtering and rectifying module is connected between the second end of the circuit breaking element and the second end of the thermistor. The capacitor is connected to the filtering and rectifying module and in parallel with the device under test. The circuit breaking element disclosed in the present invention is a multi-protector fuse and forms an open circuit when the device under test forms a short circuit. Meanwhile, the multi-protector fuse is able to withstand voltage between its first and second end without generating any physical damage.
SWITCH-MODE POWER SUPPLIES INCLUDING THREE-LEVEL LLC CIRCUITS
A switch-mode power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for supplying a direct current (DC) voltage output to a load, and a three-level LLC circuit coupled between the pair of input terminals and the pair of output terminals. The circuit includes a first switch coupled with a first diode to define a first half-bridge and a second switch coupled with a second diode to define a second half-bridge. The power supply further includes a third switch coupled across the first diode and the second diode to short circuit the first diode and the second diode when the third switch is closed, and a control circuit including a voltage-controlled oscillator (VCO), at least one flip-flop and multiple logic gates to operate the three switches with zero-voltage switching (ZVS).
COORDINATED CONTROL METHOD AND DEVICE FOR SERIES VOLTAGE SOURCE CONVERTER VALVE GROUP
A coordinated control method for series voltage source converter valve groups comprises: allocating a total direct-current voltage reference value or a total active power reference value at the end where a direct-current electrode series voltage source converter valve group is located according to the total number of voltage source converter valve groups in series; for a direct-current voltage control end, controlling the direct-current voltage of each valve group according to the assigned direct-current voltage reference value for each valve group; for an active power control end, controlling the active power of each valve group according to the assigned active power reference value for each valve group and based on adding the active power compensation amount of the valve group which has voltage equalization effects on the valve group. Correspondingly, also providing a coordinated control device for series voltage source converter valve groups. The direct-current voltage equalization of each valve group in operation of the direct-current voltage control end or the active power control end of the series voltage source converter valve group is achieved.
CIRCUIT ARRANGEMENT, METHOD FOR OPERATING A CIRCUIT ARRANGEMENT AND ELECTROLYSIS DEVICE
A circuit arrangement and to a method for operating the circuit arrangement, particularly a circuit arrangement for the DC power supply of a plurality of parallel electrolysers, where the circuit arrangement has a rectifier which converts an input-side alternating voltage into an output-side first DC voltage. Each electrolyser is respectively connected in parallel to the output of the rectifier by a down converter converting the first DC voltage into a second DC voltage such that the second DC voltage drops over the electrolyser. Each of the down converters is controllable and/or regulatable in order to adapt the level of the second direct voltage.
RECTIFIER BRIDGE
A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.
RECTIFIER BRIDGE
A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.