A variable capacitor device comprises first and second control paths which are configured to enable differential control using first and second transistors of a same doping type in the first and second control paths, respectively, wherein the first and second transistors are configured as voltage variable resistors for tuning a capacitance of the variable capacitor device.

A differential electronic circuit (25) comprising a tuning circuit (140, 140-i) connected between a first circuit node (110) and a second circuit node (112) of the electronic circuit (25), is disclosed. The tuning circuit (140, 140-i) comprises at least one controllable circuit (150, 150-i), each comprising a first MOS transistor (152) having its drain and source connected to a common node in (156) of the controllable circuit (150, 150-i) and its gate connected to a first internal node (158) of the tuning circuit (140, 140-i), and a second MOS transistor (154) having its drain and source connected to the common node (156) of the controllable circuit (150, 150-i) and its gate connected to a second internal node (160) of the tuning circuit (140, 140-i). The tuning circuit comprises a first capacitor (170) operatively connected between the first circuit node (110) and the first internal node (158) of the tuning circuit (140, 140-i) and a second capacitor (172) operatively connected between the second circuit node (112) and the second internal node (160) of the tuning circuit (140, 140-i), and a control circuit (180) configured to provide a variably controllable bias voltage to the first and the second internal nodes (158, 160) of the tuning circuit (140, 140-i) and, to each controllable circuit (150, 150-i), a digitally controllable tuning voltage to the common node (156) of the controllable circuit (150, 150-i). An electronic apparatus and a method are also disclosed.

A VCO (voltage-controlled oscillator) includes: a resonant tank having a parallel connection of an inductor, a fixed capacitor, a variable capacitor, a first temperature compensating capacitor, and a second temperature compensating capacitor across a first node and a second node, and configured to establish an oscillation of a first oscillatory voltage at the first node and a second oscillatory voltage at the second node; and a regenerative network placed across the first node and the second node to provide energy to sustain the oscillation. The variable capacitor is controlled by a control voltage, the first temperature compensating capacitor is controlled by a first temperature tracking voltage of a positive temperature coefficient, and the second temperature compensating capacitor is controlled by a second temperature tracking voltage of a negative temperature coefficient.

An oscillator circuit includes a total of N (N2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.

An integrated circuit may include oscillator circuitry having a resonator formed from fin field-effect transistor (FinFET) devices. The resonator may include drive cells of alternating polarities and sense cells interposed between the drive cells. The resonator may be connected in a feedback loop within the oscillator circuitry. The oscillator circuitry may include an amplifier having an input coupled to the sense cells and an output coupled to the drive cells. The oscillator circuitry may also include a separate inductor and capacitor based oscillator, where the resonator serves as a separate output filter stage for the inductor and capacitor based oscillator.

The present application relates to a differential oscillator circuit. The differential oscillator circuit comprises a pair of transistors with control terminals biased by a common biasing voltage. The differential oscillator circuit further comprises a transformer having a primary coil coupled between first current terminals of the transistors and a secondary coil coupled in a closed series circuit with two varactors, which are arranged for being tuned by a first common tuning voltage. The differential oscillator circuit further comprises a series circuit comprising two further varactors coupled in series to second current terminals of the transistors. The two further varactors are arranged for being tuned by a second common tuning voltage.

An LC oscillator powering arrangement comprises an LC oscillator configured to provide an oscillating signal output; a current source configured to supply the LC oscillator with a supply current, the current source during operation being controlled by a control voltage and supplied with a supply voltage subject to supply voltage ripple; and a replication block configured to generate an amplified replica of the supply voltage ripple directly from the supply voltage and to overlay the replica on the control voltage.

An integrated circuit may include oscillator circuitry having a resonator formed from fin field-effect transistor (FinFET) devices. The resonator may include drive cells of alternating polarities and sense cells interposed between the drive cells. The resonator may be connected in a feedback loop within the oscillator circuitry. The oscillator circuitry may include an amplifier having an input coupled to the sense cells and an output coupled to the drive cells. The oscillator circuitry may also include a separate inductor and capacitor based oscillator, where the resonator serves as a separate output filter stage for the inductor and capacitor based oscillator.

An integrated circuit includes at least two identical, synchronous and independent oscillator circuits that are coupled one to one in parallel with each other at homologous oscillating nodes of the respective oscillator circuits. The coupling in parallel is made using at least one coupling track that is configured so as to not introduce any phase shift or to introduce a very small phase shift.

A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.