A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.

An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. The beam former circuit may (i) be disposed in the package, (ii) have a plurality of ports, (iii) be configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) be configured to receive the radio-frequency signals at the ports while in a receive mode. A plurality of ground bumps may be disposed between the beam former circuit and the package. The ground bumps may be positioned to bracket each port. Each ground bump may be electrically connected to a signal ground to create a radio-frequency shielding between neighboring ports.

An audio amplifier of a BTL (Bridged Tied Load) type, includes a first amplifier, a second amplifier, a first output pin connected to an output of the first amplifier, a second output pin connected to an output of the second amplifier, a first monitor pin, a second monitor pin, a current source connected to the first monitor pin and configured to be switched on and off, a switch interposed between the second monitor pin and a fixed voltage line, and a load state determination circuit configured to detect a state of a load based on a potential difference between the first monitor pin and the second monitor pin.

The apparatus relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long-Term Evolution (LTE). The disclosure relates to an apparatus including an electronic circuit for amplifying a signal. The apparatus includes a transceiver including an amplification circuit, and at least one processor coupled to the transceiver. The amplification circuit includes a first path to generate a first current corresponding to a voltage of an input signal, a second path to generate a second current corresponding to a voltage of the input signal, a separation unit to control each of the first current and the second current, a current mirror to generate a third current corresponding to the first current, and a folding unit to generate an output signal on the basis of the second current and the third current.

A driving circuit includes a first differential amplifier, wherein the first differential amplifier includes: a delay adjustment circuit that generates a second differential signal by delaying a first differential signal in response to instantaneous voltage level of the first differential signal; a differential circuit that divides a source current into a first current and a second current in response to the second differential signal; and a first load resistor and a second load resistor that generate a positive phase component and a negative phase component of the differential output signal based on the first current and the second current, wherein a third differential amplifier operates in a non-saturated region when a voltage level of the first differential signal is in an input voltage range, and operates in a saturated region when the voltage level of the first differential signal is out of the input voltage range.

An integrated amplifier device includes a main amplifier configured to be coupled to an input source. A replica amplifier is coupled to the main amplifier to provide a bias to the main amplifier. A transconductance biasing cell to the main amplifier and the replica amplifier. The transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier. A method of making an integrated amplifier device is also disclosed.

The invention relates to a gain-control stage (100) for generating gain-control signals (V.sub.c+, V.sub.c) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (V.sub.Ref) and a variable gain-control voltage signal (V.sub.GC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (V.sub.1) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (V.sub.C+, V.sub.C) in dependence on the variable gain-control voltage signal (V.sub.GC), the reference voltage signal (V.sub.Ref) and a first biasing current (I.sub.B1) that depends on the control voltage signal.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

An amplifier includes a first input transistor, a second input transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal. The first current mirror circuit is coupled to the first input transistor and the second input transistor. The second current mirror circuit is coupled to the first input transistor, the second input transistor, and the first current mirror circuit.