An apparatus, such as a coherent optical receiver, includes a trans-impedance amplifier (TIA) and a low dropout (LDO) voltage regulator circuit for providing a supply voltage to the TIA. The LDO circuit is configured to adjust the supply voltage responsive to a DC voltage at an output of the TIA. In some implementations the LDO circuit may provide only a fraction of a supply current to the TIA, with another fraction provided by a partial current replica source.

An apparatus, such as a coherent optical receiver, includes a TIA, the TIA including a cascode circuit having a cascode node. A first tunable element is connected to tunably shunt the cascode node to vary a voltage gain of the TIA, e.g., up to a first amount. Implementations of the TIA further include another tunable element connected to vary a load of the cascode circuit to vary the voltage gain, e.g., up to a second amount. A current steering circuit may be provided to vary the voltage gain up to a third amount, each of the amounts being only a fraction of a target voltage gain variation of the TIA.

There is disclosed a communication cable module including: a conductive cable; a linear amplifier connected to the conductive cable; a detector for detecting presence or absence of an input signal of the conductive cable; a first circuit having a variable-current function; and a second circuit having a common-mode voltage regulating function, wherein when the input signal is not present, the variable-current function of the first circuit reduces an output current of the linear amplifier and the common-mode voltage regulating function of the second circuit regulates an output common-mode voltage of the linear amplifier.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A variable gain amplifier capable of stabilizing an average output potential of a differential output signal, improving power efficiency over a wide range of an amplitude of the differential input signal, and suppressing deterioration of a distortion rate is provided. The variable gain amplifier includes an amplifying circuit configured to amplify a differential input signal with a gain according to a gain control signal, and a current control circuit. The amplifying circuit has a first current source supplying a source current. The current control circuit adjusts a magnitude of the source current of the first current source according to a magnitude of the gain control signal.

An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.

An apparatus include a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. The beam former circuit may (i) be disposed in the package, (ii) have a plurality of ports, (iii) be configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) be configured to receive the radio-frequency signals at the ports while in a receive mode. A plurality of ground bumps may be disposed between the beam former circuit and the package. The ground bumps may be positioned to bracket each port. Each ground bump may be electrically connected to a signal ground to create a radio-frequency shielding between neighboring ports.

An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. Each antenna element may include a dual-pole antenna having a vertical feed and a horizontal feed. The beam former circuit may be (i) disposed in the package, (ii) have a plurality of pairs of ports, (iii) configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) configured to receive the radio-frequency signals at the ports while in a receive mode. Each pair of the ports is configured to be directly connected to a respective one of the antenna elements. All of the ports may be spatially routed into alignment with the vertical feeds and the horizontal feeds in a single conductive plane of the antenna array.

An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.

An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of transceiver circuits while a corresponding one of the control signals is in an active state.

The transceiver circuits may be updated with the setting values from the registers within a predetermined time.