A power amplifying circuit includes a switching circuit, an amplifier and a load. The switching circuit receives a first supply voltage and a second supply voltage. When the switching circuit is in a first operation mode, the first supply voltage is provided to a node. When the switching circuit is in a second operation mode, the second supply voltage is provided to the node. The amplifier receives a first input signal and a second input signal, and outputs a first output signal and a second output signal from a first output terminal and a second output signal, respectively. The load includes a first inductor and a second inductor. The first inductor is connected between the node and the first output terminal. The second inductor is connected between the node and the second output terminal.

An electronic device including an amplifier which includes a first transistor configured to receive an input signal through a gate terminal thereof and having a source terminal electrically connected to ground, a second transistor configured to transmit an output signal through a drain terminal thereof and having a gate terminal electrically connected to the ground, and a switch electrically connected to the gate terminal of the second transistor and configured to switch a voltage being supplied to the gate terminal of the second transistor in accordance with turn-on or turn-off of the amplifier.

A novel and useful linear, efficient, smart wideband CMOS hybrid power amplifier that combined an analog linear amplification path and a digital power amplification (DPA) path. PA path control logic analyzes the input I and Q signals and determines which amplification paths to steer the input I and Q signals to. The analog linear amplification path comprises digital to analog converters for both I and Q paths and one or more analog linear power amplifiers. The digital power amplification path comprises I and Q up-sampling circuits and I and Q RF DAC circuits (e.g., digital PA circuits). In operation, the PA path control logic compares the I and Q signals to thresholds (which may or may not be different) and based on the comparisons, selects one or more paths for the input I and Q signals. Whether the signals from the analog and digital amplification paths are to be combined or selected (i.e. switched), the PA path control circuit is operative to generate select (switch) control signals which are applied to summer/selector elements which generate the output of the hybrid PA.

The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.

The disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as long term evolution (LTE). An operation method of a device for upconversion in a wireless communication system is provided. The method includes receiving a first local oscillator (LO) signal, generating a second LO signal, based on the first LO signal and cross-coupled latches, receiving an input signal, generating an upconverted frequency, based on the second LO signal and the input signal, generating an output signal obtained by processing a harmonic component included in the upconverted frequency, and transmitting the generated output signal.

A cascode structure, an output structure, an amplifier and a driving circuit are provided. A bias voltage of a common-gate structure in the cascode structure is provided by the cascode structure, bias voltages of transistors in the output structure are all provided by the output structure, the amplifier includes the cascode structure and/or the output structure described above, the driving circuit includes the amplifier described above.

The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.

An amplifier including a first cascode circuit including a first transistor and a second transistor whose source or emitter is coupled to a drain or a collector of the first transistor, a second cascode circuit being a differential pair with the first cascode circuit, the second cascode circuit including a third transistor whose source or emitter is coupled to a source or an emitter of the first transistor and a fourth transistor whose source or emitter is coupled to a drain or collector of the third transistor, a first feedback path that couples between an output terminal of the third transistor and an input terminal of the first transistor, the first feedback path including a first capacitative element, and a second feedback path that couples between an output terminal of the first transistor and an input terminal of the third transistor, the second feedback path including a second capacitative element.

Disclosed examples include a radar system that operates in a first mode and a second mode. In the first mode, the system detects the presence of an object within a threshold range. In response to detection of the presence of the object, the system transitions to the second mode, and the system generates range data, velocity data, and angle data of the object in the second mode. When the object is no longer detected within the threshold range, the system transitions back to the first mode.

A circuit includes a first transistor comprising a gate, a source, and a drain, and an inductor coupled between the gate and the source of the first transistor, wherein the source is further coupled to a current source and the gate is further coupled to an amplifier.