H03F3/45192

SEMICONDUCTOR AMPLIFIER CIRCUIT AND SEMICONDUCTOR CIRCUIT
20210044257 · 2021-02-11 ·

A semiconductor amplifier circuit has a driver that outputs a drive signal corresponding to an input signal and switches drive capability of the drive signal in accordance with a logic of an instruction signal, an instruction signal setting unit that sets the logic of the instruction signal in accordance with whether the input signal satisfies a predetermined condition, and an output circuit that comprises a control terminal to which the drive signal is input and an output terminal that outputs a signal obtained by amplifying the input signal.

Mute mechanism with reduced pop noise in audio amplifier systems and methods

Systems and methods are provided for improved noise performance of audio amplifiers. In one example, a system includes a multistage amplifier comprising at least a first stage amplifier and a second stage amplifier. The system further includes a plurality of switches disposed within the multistage amplifier to configure the multistage amplifier. The system further includes a control signal configured to control the multistage amplifier to a normal amplification mode or a mute state, wherein the multistage amplifier is adapted to amplify an input signal in the normal amplification mode, the multistage amplifier is adapted to output a zero signal in the mute state, and internal amplification stages of the multistage amplifier are disabled in the mute state, and output stages of each of the at least first stage amplifier and the second stage amplifier are electrically shorted and/or shorted to a fixed bias voltage in the mute state.

Offset voltage trimming for operational amplifiers

An operational amplifier is disclosed. The operational amplifier activates/couples either a first or a second differential pair of transistors to an input based on the input voltage. The first and second pair of transistors are each biased with a current having a first portion that is constant with temperature and a second portion that is proportional to temperature. By adjusting the ratios of the first and second portions, the transconductance of each differential pair may be made relatively constant with temperature. Each differential pair is coupled to a trim current source that is adjusted to reduce the voltage offset at each output. The resulting voltage offset for the operational amplifier is relatively constant over a range of input voltages and has temperature coefficient unaffected by the trimming process.

SOLID-STATE CHARGE DETECTOR

The present invention is a system and method for providing a charge detector that utilizes small feedback capacitors in a low-noise, high-gain, system that combines a differential topology in a solid-state amplifier implemented in a complementary metal-oxide semiconductor (CMOS) process with active reset, thereby achieving high dynamic range and robust operations. A custom optoelectronic system is used to measure gain, and while operating at a sampling frequency of 10 kHz, the active reset extends the dynamic range of the charge detector.

DC-DC CONVERTER
20210067038 · 2021-03-04 ·

A DC-DC converter according to an embodiment is a DC-DC converter for generating an output voltage VOUT according to a reference voltage VREF, and includes a fully differential amplifier that outputs a first differential output signal and a second differential output signal according to a differential input using the reference voltage VREF and the output voltage VOUT, a pulse width modulation signal generation circuit that generates a pulse width modulation signal based on the first differential output signal Vout1 and the second differential output signal Vout2, and a driver that outputs a driving signal obtained by waveform-shaping the pulse width modulation signal.

Slew boost circuit for an operational amplifier

A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

AMPLIFIER DEVICE AND OFFSET CANCELLATION METHOD
20210091736 · 2021-03-25 ·

An amplifier device includes an amplifier circuitry, a controller circuitry, and an offset cancellation circuitry. The amplifier circuitry is configured to amplify a first input signal and a second input signal, in order to generate a first output signal and a second output signal. The controller circuitry is configured to generate a first control signal and a second control signal according to the first output signal and the second output signal. The offset cancellation circuitry is configured to provide a negative capacitor to the amplifier circuitry, and to adjust at least one current flowing through a circuit, which provides the negative capacitor, of the offset cancellation circuitry according to the first control signal and the second control signal, in order to cancel an offset of the amplifier circuitry.

AMPLIFIER

An amplifier includes: a first input transistor connected to a first input, a first output, and a power source or a ground, a second input transistor connected to a second input, a second output, and the power source or the ground; a first replica transistor connected to the first input, a detection node, and the power source or the ground; a second replica transistor connected to the second input, the detection node, and the power source or the ground; and a bias transistor connected to a bias voltage, the detection node, and the power source or the ground.

Fully Differential Rail-to-Rail Output Amplifier with Inverter-Based Input Pair
20210013851 · 2021-01-14 ·

A fully differential rail-to-rail-output amplifier includes a differential input inverter pair, folded cascode pair, class AB control pair, and class AB output rail-to-rail pair. A drain associated with the folded cascode pair is operatively coupled to the class AB control pair, and the drain associated with the folded cascode pair is unconnected to the current source associated with the class AB control pair. A method of providing fully differential rail-to-rail-output amplification includes coupling a folded cascode pair operatively to a differential input inverter pair, coupling a drain associated with the folded cascode pair operatively to a class AB control pair, and coupling a class AB output rail-to-rail pair operatively to the class AB control pair.

ELECTRONIC CIRCUIT FOR CONFIGURING AMPLIFYING CIRCUIT CONFIGURED TO OUTPUT VOLTAGE INCLUDING LOW NOISE

An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.