The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.

A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

The disclosed embodiments relate to the design of a system that implements an up-conversion mixer. This system includes a regulator-based linearized transconductance (g.sub.m) stage, which converts a differential intermediate frequency (IF) voltage signal into a corresponding pair of IF currents. It also includes a pair of current mirrors, which duplicates the pair of IF currents into sources of a set of switching transistors. The set of switching transistors uses a differential local oscillator (LO) signal to gate the duplicated pair of IF currents to produce a differential radio frequency (RF) output signal. Finally, a combination of capacitors and/or inductors is coupled to common source nodes of the set of switching transistors to suppress higher order harmonics in an associated common source node voltage signal.

Provided are a transmitting device connected to a receiving device via a channel and the receiving device connected to the transmitting device via a channel. The transmitting device connected to a receiving device includes: a transmitter connected to the channel via an output node and configured to transmit, via the channel, a transmission signal to the receiving device, the transmitter having a transmission impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a receiving impedance of the receiving device by monitoring a voltage level of the output node, the monitoring device configured to set the transmission impedance based on the channel impedance and the receiving impedance.

A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

The invention provides a Low-voltage Differential Signaling (LVDS) receiver circuit that comprises a folded-cascode operational transconductance amplifier (OTA) that includes a pair of input branches and a pair of output branches. The pair of input branches of the folded-cascode OTA includes a p-channel metal-oxide semiconductor (PMOS) input transistor pair connected to a first supply voltage domain. The pair of output branches includes an output circuit connected to a second supply voltage domain. The LVDS receiver circuit further includes a common-mode feedback circuit connected to the pair of output branches of the folded-cascode OTA that controls the second supply voltage domain. The LVDS receiver circuit further includes a regenerative buffer circuit connected to the pair of output branches of the folded-cascode OTA and an output generated from the pair of output branches of the folded-cascode OTA directly operates the regenerative buffer circuit to produce a distortion-free output signal.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.