Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

The present disclosure discloses a startup circuit device, a filter and a receiver. The startup circuit device is applicable to the filter that includes a fully-differential operational amplifier and a common-mode feedback circuit device connected in sequence. Both the first startup input terminal and the first startup output terminal are connected to a first amplification input terminal of the fully-differential operational amplifier, and both the second startup input terminal and the second startup output terminal are connected to a second amplification input terminal of the fully-differential operational amplifier. The startup circuit device is configured to adjust a received input voltage to a target voltage during startup of the fully-differential operational amplifier, and output the target voltage to the fully-differential operational amplifier, such that the fully-differential operational amplifier operates at the target voltage, and stability of the fully-differential operational amplifier during the startup can be improved effectively.

A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

A circuit includes first through fourth transistors and a device. The first transistor has a control input and first and second current terminals. The control input provides a first input to the circuit. The second transistor has a control input and first and second current terminals. The control input provides a second input to the circuit. The third transistor has a control input and first and second current terminals. The fourth transistor has a control input and first and second current terminals. The second current terminal of the fourth transistor is coupled to the second current terminal of the third transistor, and the control input of the fourth transistor is coupled to the first current terminals of the first and second transistors. The device is configured to provide a fixed voltage to the control input of the third transistor.

The present invention is a system and method for providing a charge detector that utilizes small feedback capacitors in a low-noise, high-gain, system that combines a differential topology in a solid-state amplifier implemented in a complementary metal-oxide semiconductor (CMOS) process with active reset, thereby achieving high dynamic range and robust operations. A custom optoelectronic system is used to measure gain, and while operating at a sampling frequency of 10 kHz, the active reset extends the dynamic range of the charge detector.

A DC-DC converter according to an embodiment is a DC-DC converter for generating an output voltage VOUT according to a reference voltage VREF, and includes a fully differential amplifier that outputs a first differential output signal and a second differential output signal according to a differential input using the reference voltage VREF and the output voltage VOUT, a pulse width modulation signal generation circuit that generates a pulse width modulation signal based on the first differential output signal Vout1 and the second differential output signal Vout2, and a driver that outputs a driving signal obtained by waveform-shaping the pulse width modulation signal.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit amplifies a voltage difference between its input terminals, to generate plural pre-stage transconductance currents flowing through corresponding plural pre-stage transconductance nodes. The floating control circuit includes: a floating reference transistor configured as a source follower and a floating amplifier. The floating amplifier and the floating reference transistor are coupled to form feedback control and to generate an upper driving signal and a lower driving signal according to a floating reference level in the floating control circuit. The upper driving signal is higher than the lower driving signal with a predetermined voltage difference. The floating control circuit is electrically connected to the plural pre-stage transconductance nodes and is floating in common mode relative to the pre-stage transconductance nodes.

An equalizer having a split folded cascode architecture includes a circuit having a differential pair with a single tail current source and split folded cascode branches. The single tail current source eliminates the input referred offset due to a mismatch in current sources. The folded cascode amplifier acts as the equalizer, which is split into a derivative path and a proportional path. The derivative path boosts the high frequency components of the received signal. The gain of the low frequency components of the received signal is adjusted by the proportional path. The derivative path includes variable capacitors and variable resistors which allow fixing a ‘zero’ frequency and peak gain frequency to a predetermined value, wherein frequencies greater than the ‘zero’ frequency are boosted. The proportional path includes variable resistors, which allow adjusting the low frequency gain without affecting the ‘zero’ frequency and peak gain frequency.

In an embodiment a differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.