According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

An output stage circuit of an operational amplifier, the operational amplifier, and a signal amplifying method applied to the operational amplifier are provided. The output stage circuit includes an inverting circuit and a compensation module. The inverting circuit is electrically connected to a gain stage circuit of the operational amplifier. The inverting circuit generates an output signal of the operational amplifier. The compensation module includes a first compensation circuit, including a first current providing path and a first suppression activation circuit. The first current providing path provides a first compensation current. The first suppression activation circuit conducts the first compensation current to the inverting circuit if a first compensation condition related to a first gain stage signal generated by the gain stage circuit is satisfied. Variation of the output signal is suppressed because of the first compensation current.

Systems and methods for providing a high performance current source are described. In an example implementation, the current source includes transistors in dual current mirror configuration. The dual mirror configuration employs current feedback to increase the output resistance of the current source while achieving a wide voltage swing.

A technique for receiving a DC or low frequency input signal using a chopper-stabilized amplifier includes chopping an input signal using a chopper clock signal to generate a chopped input signal. The input signal has a first voltage range and the chopper clock signal has a second voltage range. The chopper clock signal has peak-to-peak voltage over a period of the chopper clock signal. The peak-to-peak voltage is less than the first voltage range and is less than the second voltage range. A frequency of the input signal is at least an order of magnitude less than a frequency of the chopper clock signal. The second voltage range may be greater than or equal to the first voltage range. The technique may include generating a bias signal based on a voltage reference signal and an output signal having the first voltage range.

An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.

According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. The fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

According to one embodiment, an operational amplifier includes first and second input terminals, an output terminal, differential circuitry, and output circuitry. The differential circuitry including first and second nodes, and first and second transistors. The output circuitry including third through fifth nodes, and third through eighth transistors. The third transistor being coupled to the first node at a gate and coupled to the third node at one end. The fourth transistor being coupled to the second node at a gate and coupled to the fourth node at one end. The fifth transistor being coupled to the fourth node at a gate and coupled to the third node at one end. The sixth transistor being coupled to the fourth node at each of a gate and one end.

An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.