An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

Logarithmic current-to-voltage converters with emitter resistance compensation are disclosed herein. In certain embodiments, a logarithmic current-to-voltage converter includes a logarithmic bipolar transistor that converts an input current to a logarithmic voltage, and an emitter resistance compensation circuit that includes a replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit processes a copy of the input current to generate an emitter resistance compensation signal that adjusts the logarithmic voltage to correct for an error introduced by an emitter resistance of the logarithmic bipolar transistor. By providing emitter resistance compensation in this matter, logarithmic current-to-voltage conversion with high accuracy and low log error is achieved.

Various aspects of this disclosure describe reducing distortion of a power amplifier by coupling a common mode signal, such as determined from a voltage supply signal of the power amplifier or output of the power amplifier, to an input of the power amplifier. A resistive digital-to-analog converter (DAC) can be coupled to the power amplifier, and a common mode signal is modulated onto differential reference voltages of the DAC, causing the common mode signal to exist at both the input and output of the power amplifier at approximately the same time. Consequently, current flowing at differential inputs of the power amplifier due to the common mode component drops to zero, causing distortions due to common mode to differential mode conversion to be reduced.

The present invention provides a built-in ripple injection circuit and a control chip, in which a divided feedback voltage is obtained by division of an output voltage by a feedback circuit, and high-frequency ripple in the output voltage is obtained by an operational amplifier and a first capacitor. Moreover, the high-frequency ripple is injected at a third terminal of a source follower. As a result, the feedback voltage is a superimposition of the divided feedback voltage with the high-frequency ripple. This can enhance stability and interference resilience of a power supply system operating in a ripple-based COT control mode. Further, the built-in ripple circuit can be integrated in the control chip. This dispenses with the use of a large capacitor and satisfactorily addresses applications requiring on-chip integration of the feedback circuit, reducing the cost of the power supply system.

A baseline restorer circuit including a controller; a sample control circuit arranged to receive an input voltage signal that is output from a circuit stage comprising an amplifier, and configured to capture a sample of the input voltage signal at a sampling time in response to receiving a control signal from the controller; an analogue processing stage to receive the sample and a constant baseline reference voltage and selectively process the sample to provide an output voltage; a transconductance stage to convert the output voltage to a compensation current and supply the compensation current to an input of the circuit stage; and a change detector to monitor if the input voltage signal changes during a time interval around the sampling time, and if no change is detected in the input voltage signal during the time interval, the controller is configured to control the analogue processing stage to process the sample.

A signal processing circuit, including: first and second operational amplifiers, each configured to perform offset adjustment and being selectable to operate as an amplifier circuit to output an output voltage; a comparator circuit comparing the output voltage and a predetermined voltage; and a control circuit that, upon completion of the offset adjustment of the first operational amplifier, causes the first operational amplifier to process an input signal, while causing the second operational amplifier to stop processing the input signal and perform the offset adjustment in response to a signal of a period, and upon completion of the offset adjustment of the second operational amplifier, causes the second operational amplifier to process the input signal, while causing the first operational amplifier to stop processing the input signal and to perform the offset adjustment in response to the signal of the period, each based on a comparison result of the comparator circuit.