A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.

A circuit for implementing a differential input receiver is described. The circuit comprises an input circuit having a first input node and a second input node configured to receive a differential input signal; a first output circuit having a first capacitor coupled between the first input node and a first output node and a second capacitor coupled between the second input node and a second output node, wherein the first output circuit generates an output signal at the first output and the second output when the input signal is in a first frequency range; and a second output circuit comprising an amplifier having a first amplifier input coupled to the first input node and a second amplifier input coupled to the second input node, wherein the second output circuit generates an output signal when the input signal is in a second frequency range which extends lower than the first frequency range. A method of implementing a differential input receiver is also described. The circuits and methods also allow for offset compensation.

A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.

A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.

A current sense circuit may comprise a first circuit node and a second circuit node configured to be coupled to a first terminal and a second terminal of a current sense resistor, respectively; differential amplifier including a first input and a second input which are coupled to the first circuit node and the second circuit node via a first input resistor and a second input resistor; a voltage source, configured to set the voltage at the first input of the differential amplifier; and a controllable current mirror configured to sink or source a first current in its input branch based on one or more outputs of the differential amplifier and to generate a corresponding second current in its output branch. The input branch is coupled to the second input of the differential amplifier. A biasing circuit is coupled to the controllable current mirror.

The overall performance of a current sense amplifier system may be improved by increasing the common mode rejection of the system. In particular, improved current sense amplifier systems of this disclosure may be configured to use a first ADC path to measure a current flowing through a device, a second ADC path to measure a common mode value, a memory element to store a calibration value, and a summer block to output a voltage proportional to the measured current through the device by correcting a voltage value output by the first ADC path based on the measured common mode value of the second ADC path and the stored calibration value.

The overall performance of a current sense amplifier system may be improved by increasing the common mode rejection of the system. In particular, improved current sense amplifiers may be configured to use a first signal path coupled to the amplifier and a first input terminal, wherein the first signal path is configured to measure the current through a device by generating a voltage proportional to the measured current, wherein the generated voltage comprises a small signal voltage with a large common mode voltage, and a second signal path coupled to the amplifier and the first input terminal, wherein the second signal path is configured to reduce the common mode of the generated voltage by level shifting the generated voltage to reduce the common mode voltage.

A microphone preamplifier circuit is adapted to be connected to a microphone circuit, the microphone circuit including a microphone and at least one output node. The microphone preamplifier circuit includes a preamplifier including: an operational amplifier having at least one input and at least one output; at least one input DC decoupling capacitor connected to the at least one input of the operational amplifier; at least one feedback capacitor connected between the input and the output of the operational amplifier in order to set together with the at least one input DC decoupling capacitor a gain value of the preamplifier circuit; and first and second feed nodes adapted to be fed by first and second bias voltages respectively. The preamplifier further includes at least one switched capacitor adapted to be selectively and alternatively connected in response to a clock signal: between the at least one input and the at least one output of the operational amplifier; and between the first and second feed nodes. The microphone preamplifier circuit further includes an anti-aliasing filter having: (i) at least one output terminal connected to the at least one input DC decoupling capacitor and (ii) at least one input terminal adapted to be connected to the at least one output node of the microphone circuit.

A radio frequency front-end (RF-FE) device with a reconfigurable common-mode feedback control. The device includes a plurality of RF-FE channels and a reconfiguration switch. An RF-FE channel includes a common-mode feedback loop. The common-mode feedback loop is configured to detect a common-mode signal in differential signals in the RF-FE channel and generate a feedback signal to set the common-mode signal. The reconfiguration switch is configured to couple common-mode feedback loops of two or more RF-FE channels based on an operation mode. The reconfiguration switch may be controlled to couple common-mode feedback loops of two or more RF-FE channels if the two or more RF-FE channels receive a same input signal and decouple common-mode feedback loops of two or more RF-FE channels if the two or more RF-FE channels receive different input signals.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a 5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise/fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a 10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise/fall timing and 8 to 12 nanosecond minimum pulse widths.