An apparatus performs interpolation/decimation in a digital circuit that receives an input signal and includes upsampling/downsampling and filtering stages. First and second paths include distinct first and second portions of the upsampling/downsampling and filtering stages. The first path consumes less quiescent state power. A selection circuit uses the first or second path and turns off the unused first or second path based on input signal spectral content or level. A mode includes applying a front-end digital/analog gain and a corresponding back-end analog/digital attenuation in conjunction with the first path being used and the second path being turned off. A cross-fader uses the first and second paths in a weighted mix manner while making a transition between using the first and second paths. The second path has higher filtering performance (e.g., superior stopband attenuation, passband ripple, transition band, e.g., via higher order or greater bit-width filtering).

As part of a signal processing event, the maximum frequency of an input signal can be determined with a processor. The maximum frequency can be compared to a value generated with a decimator/interpolator. Based on the comparison, the sampling rate for sampling the input signal with the processor can be set as part of the digital signal processing event. The sampling rate can be adjusted as the frequency of the input signal varies during the signal processing event.

An apparatus performs interpolation/decimation in a digital circuit that receives an input signal and includes upsampling/downsampling and filtering stages. First and second paths include distinct first and second portions of the upsampling/downsampling and filtering stages. The first path consumes less quiescent state power. A selection circuit uses the first or second path and turns off the unused first or second path based on input signal spectral content or level. A mode includes applying a front-end digital/analog gain and a corresponding back-end analog/digital attenuation in conjunction with the first path being used and the second path being turned off. A cross-fader uses the first and second paths in a weighted mix manner while making a transition between using the first and second paths. The second path has higher filtering performance (e.g., superior stopband attenuation, passband ripple, transition band, e.g., via higher order or greater bit-width filtering).

A receiving device includes: a resampler to convert a sampling rate of a reception signal, and output a first signal that is a signal having been subjected to sampling rate conversion; an equalizer to perform an adaptive equalization process using the first signal as an input, and output a second signal that is a signal having been subjected to the adaptive equalization process and having a sampling rate that is an integer fraction of an input signal; a correlation calculator to calculate a correlation function between the first signal and the second signal; and a rate controller to control a rate conversion ratio for sampling rate conversion in the resampler on a basis of the correlation function.

A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate f.sub.S for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate f.sub.samp, the first clock rate f.sub.S being N times greater than the second clock rate f.sub.samp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate f.sub.samp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

A method of increasing the sample rate of a digital signal by creating intermediate sample points between adjacent neighbouring sample points comprising the step of populating each of the intermediate sample points depending on a weighted influence of a predetermined number of the neighbouring sample points, the weighted influence being calculated by representing the digital signal or filter at the predetermined number of sample points at least in part by its cosine components, which are each represented by absolute values of a cosine function in the time domain substantially limited to half a waveform cycle at its mid-point; combining the aforementioned cosine components at each of the neighbouring sample points to obtain waveforms at each of the neighboring sample points; determining values for each of the waveforms at the intermediate sample points and combining the determined values at the intermediate sample point to derive the weighted influence.

A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.

Integrated circuit devices, methods, and circuitry for implementing and using a flexible circuit for real and complex filter operations are provided. An integrated circuit may include programmable logic circuitry and digital signal processor (DSP) blocks. The DSP blocks may be configurable to receive inputs from the programmable logic circuitry and may include first and second multiplier pairs. The first multiplier pair may include a first multiplier that may receive a first input and a second input and a second multiplier that may receive the second input and a third input of the inputs. The second multiplier pair may include a third multiplier that may receive the first input or a fourth input and a fifth input and a fourth multiplier that may receive the third input or a fifth input and a sixth input.

A communication system using adaptive sample rate reduction (ASRR) is disclosed. The system includes a digital front end (DFE) and a radio frequency (RF) interface. The DFE is configured to receive a baseband signal, identify reduced performance parameters for the baseband signal, reduce a sampling rate for the baseband signal based on the reduced performance parameters and generate a digital interface signal using the reduced sampling rate. The RF interface is configured to generate an analog TX signal from the digital interface signal.

A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.