An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a flip-flop having a gated input circuit and a transmission gate. The first time delay circuit is configured to receive a first clock signal and to output a second clock signal. The second time delay circuit is configured to receive the second clock signal and to output a third clock signal. The transmission gate is controlled with the first clock signal and the second clock signal. The gated input circuit is controlled by the third clock signal. The first time delay circuit includes a first gate via-connector in direct contact with a first gate-conductor which intersects a first-type active region structure in a first area. The second time delay circuit includes a second gate via-connector in direct contact with a second gate-conductor which intersects a second-type active region structure in a second area.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a flip-flop having a gated input circuit and a transmission gate. The first time delay circuit is configured to receive a first clock signal and to output a second clock signal. The second time delay circuit is configured to receive the second clock signal and to output a third clock signal. The transmission gate is controlled with the first clock signal and the second clock signal. The gated input circuit is controlled by the third clock signal. The first time delay circuit includes a first gate via-connector in direct contact with a first gate-conductor which intersects a first-type active region structure in a first area. The second time delay circuit includes a second gate via-connector in direct contact with a second gate-conductor which intersects a second-type active region structure in a second area.