High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.

A dynamic single input-dual output latch includes input, feedback, and output stages. In the input stage, operations are dependent on a clock signal (CLK) and a feedback signal (FB) from the feedback stage. For example, when FB is at a low voltage level and CLK switches to a high voltage level, the input stage enters a data capture mode. Once data has been captured, FB switches back to the high voltage level, placing the input stage in a data hold mode. In the output stage, operations are dependent on CLK but independent of FB. For example, instead of initiating output signal stabilization only after both CLK and FB are at high voltage levels, weak pull-down transistors (including at least one CLK-controlled pull-down transistor) are employed in the output stage to ensure output signal stabilization is initiated after data capture has begun but before FB switches to the high voltage level.

A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

A comparing device includes a first current generating circuit arranged to selectively generate a first current and a second current different from the first current, according to a first control signal. The comparing device also includes a comparing circuit having a common node coupled to the first current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

A comparing device includes: a first current generating circuit arranged to selectively generate a first current according to a first control signal; a second current generating circuit arranged to generate a second current; and a comparing circuit having a common node coupled to the first current generating circuit and the second current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal.

The invention relates to a high-speed decision device that comprises a first branch and a second branch that are connected in parallel between a power supply end and a clock signal input end; wherein the first branch is used for providing a normal-phase input end, and the second branch is used for providing an inverted-phase input end; a first adjusting point and a second adjusting point are arranged; and an adjusting branch is arranged between the first adjusting point and the second adjusting point, and the adjusting branch is used for adjusting the response speed when the clock signal changes. The benefit of the invention is that the response time of the circuit is further improved, the resolution of the high-speed decision device is improved, and the clock and data recovery performance of the high-speed decision device is further improved.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A level shifter is disclosed. The level shifter comprises a pulse generating circuit, configured to receive an input signal, and generate a plurality of first-level pulses having a pulse width shorter than a pulse width of the input signal, wherein the input signal swings over a first voltage domain; a pulse transforming circuit, coupled to the pulse generating circuit, configured to generate a plurality of second-level pulses corresponding to the plurality of first-level pulses; and a latching circuit, coupled to the pulse transforming circuit, configured to generate an output signal by latching a status of the output signal in response to the plurality of second-level pulses, wherein the output signal swings over a second voltage domain.