A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

The present document relates to a level shifter circuit configured to transform an input voltage at an input of the level shifter circuit into an output voltage at an output of the level shifter circuit. The level shifter circuit may comprise a first switching element coupled between an output supply voltage and a positive output terminal, wherein a control terminal of the first switching element is coupled to a negative output terminal. The level shifter circuit may comprise a second switching element coupled between the output supply voltage and the negative output terminal, wherein a control terminal of the second switching element is coupled to the positive output terminal. The level shifter circuit may comprise a drive circuit configured to drive the control terminals of the first and the second switching element based on the input voltage at the input of the level shifter circuit.

Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.

It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising: i) a multiplier device (110), configured to receive a single-ended incoming signal (105), and multiply the incoming signal (105) to provide a multiplied signal (115); and ii) a divider device (120), configured to receive the multiplied signal (115), and divide the multiplied signal (115) to provide a differential signal (125a, 125b).

Further, a corresponding signal conversion method is described.

One or more examples relate to voltage level shifting. An example apparatus may include first and second inputs, an output, and a circuit. The first and second inputs may receive compliments of a signal represented by first voltage levels. The output may provide the signal represented by second voltage levels. The circuit may change voltage levels utilized to represent the signal from first voltage levels to second voltage levels. The circuit may include cross-coupled first high voltage switches, a pair of series coupled switches, and a pair of voltage clamping switches. The cross-coupled first high voltage switches may selectively couple the output to a high voltage node responsive to a high voltage level of the signal. The pair of series coupled switches may comprising respective second high voltage switches, and the pair of series coupled switches may selectively couple the output to a first voltage supply. The pair of voltage clamping switches may increase OFF-resistance of the respective second high voltage switches of the pair of series coupled switches responsive to a low voltage level at the respective input.

In the present invention, a differential amplifier that includes a first output transistor and a second output transistor includes a boost circuit that includes a third output transistor and a fourth output transistor. The first output transistor delivers a current according to a first differential signal generated in a differential stage to an output terminal. The second output transistor extracts a current according to a second differential signal generated as a signal which is the same phase with a different potential of the first differential signal from the output terminal. The third output transistor delivers a current to the output terminal according to a level-shifting signal generated by level-shifting the first differential signal. The fourth output transistor extracts a current from the output terminal according to a level-shifting signal generated by level-shifting the second differential signal. As the third and fourth output transistors, transistors having withstand voltages against gate-source voltages lower than those of the first and second output transistors and drain currents larger than those of the first and second output transistors are employed.

Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.

A semiconductor device includes an I/O circuit configured to be supplied with a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage, and to receive an input signal based on the first voltage. The I/O circuit includes an enabler circuit configured to be supplied with the second voltage, and to generate a first signal based on the second voltage, and a first level shifter circuit coupled to the enabler circuit, and configured to, based on the first signal, level-shift a signal based on the second voltage to a signal based on the third voltage.