Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.

Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.

A signal receiver circuit includes: a negative voltage applier suitable for applying a negative voltage to a common source node in response to a first clock is at a first logic level; a first sampling transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock is at a second logic level; a precharger suitable for precharging a first output node and a second output node with a pull-up voltage in response to a second clock is at the first logic level, and electrically coupling the first output node and second output node to the second sampling node and the first sampling node, respectively, in response to the second clock is at the second logic level; and an amplifier suitable for amplifying a voltage difference between the first output node and the second output node in response to the second clock is at the second logic level.

A semiconductor integrated circuit includes a sense amplifier circuit suitable for generating differential output signals by sensing and amplifying a level difference of differential input signals in response to a clock signal, and outputting the differential output signals to first and second nodes, respectively, a latch circuit suitable for feeding back and latching the differential output signals between the first and second nodes, and a control circuit suitable for controlling the feedback of the differential output signals between the first and second nodes in response to an initialization signal.

A latch circuit includes a switch circuit, an input circuit, and an output circuit. The switch circuit is coupled between a first power node and a second power node, and includes a non-inverting output node and an inverting output node. The input circuit couples with the non-inverting output node and the inverting output node, and conducts the non-inverting output node with the second power node according to a clock signal and a data signal. The output circuit couples with the non-inverting output node, the inverting output node, the first power node, and the second power node. The output circuit conducts the non-inverting output node with the first power node according to the clock signal and the data signal. When the data signal is switched, the switch circuit sets a conductive path from the first power node to the second power node as an open circuit.

A signal receiver circuit includes: a negative voltage applier suitable for applying a negative voltage to a common source node in response to a first clock is at a first logic level; a first sampling transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock is at a second logic level; a precharger suitable for precharging a first output node and a second output node with a pull-up voltage in response to a second clock is at the first logic level, and electrically coupling the first output node and second output node to the second sampling node and the first sampling node, respectively, in response to the second clock is at the second logic level; and an amplifier suitable for amplifying a voltage difference between the first output node and the second output node in response to the second clock is at the second logic level.

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.

A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.

A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.