A ramp signal generation device includes a sampling circuit suitable for sampling a ramp current and storing a voltage corresponding to the sampled ramp current; a current maintaining circuit suitable for maintaining the ramp current; a current transferring circuit suitable for transferring a current corresponding to the voltage stored on the sampling circuit; and a current-to-voltage converter suitable for converting and generating a ramp voltage corresponding to the current transferred from the current transferring circuit.

An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

A small area oscillator circuit is provided. The oscillator circuit includes first and second constant current sources, a comparator, first and second capacitive elements, and a resistive element. In a first state, the first capacitive element is connected to the first constant current source and the fixed voltage node, the second capacitive element is connected to the second constant current source and the first current source, and resistive element is connected to the second constant current source. In a second state, the first capacitive element is connected to the second constant current source and first constant current source, the second capacitive element is connected to the second constant current source and the fixed voltage node, and the resistive element is connected to the first constant current source.

A small area oscillator circuit is provided. The oscillator circuit includes first and second constant current sources, a comparator, first and second capacitive elements, and a resistive element. In a first state, the first capacitive element is connected to the first constant current source and the fixed voltage node, the second capacitive element is connected to the second constant current source and the first current source, and resistive element is connected to the second constant current source. In a second state, the first capacitive element is connected to the second constant current source and first constant current source, the second capacitive element is connected to the second constant current source and the fixed voltage node, and the resistive element is connected to the first constant current source.

Various embodiments relate to a single slope analog to digital converter (ADC), including: a voltage slope generator configured to generate a voltage slope based upon a fixed current and variable current; an analog comparator configured to compare a voltage to a voltage output from the voltage slope generator; a first register configured to store a first count based upon a reference voltage being input into the analog comparator; a second register configured to store a second count based upon an input voltage being input into the analog comparator, wherein the input voltage is the voltage to be converted to a digital value by the ADC; and a digital to analog converter (DAC) configured to produce a slope trim signal based upon the voltage slope output by the voltage slope generator, the first count, and a count target associated with the voltage reference, wherein the variable current in the voltage slope generator is based upon the slope trim signal.

A method of operating a relaxation oscillator includes determining a measure of a propagation delay of a detection device of a relaxation oscillator and increasing a charging rate of a capacitor device of the relaxation oscillator for a time duration based on the determined measure of the propagation delay.

A method of operating a relaxation oscillator includes determining a measure of a propagation delay of a detection device of a relaxation oscillator and increasing a charging rate of a capacitor device of the relaxation oscillator for a time duration based on the determined measure of the propagation delay.

Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.