A count value generation circuit includes a first counter that counts edges of a reference signal to generate a first count value in synchronization with an input signal, a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal, a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value, and a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.

An integrated circuit comprising (1) an array of logic tiles including a first and a second plurality of logic tiles, wherein each logic tile of the array is configurable to electrically connect with at least one other logic tile, and (2) a clock mesh fabric to provide a mesh clock signal to the first plurality of the logic tiles. Each logic tile of the first plurality includes clock distribution and transmission circuitry including: (1) tile clock generation circuitry configurable to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals of each logic tile of the first plurality of logic tiles, and (2) clock selection circuitry configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock to the circuitry which performs operations using or based on the associated tile clock.

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

A count value generation circuit includes a first counter that counts edges of a reference signal to generate a first count value in synchronization with an input signal, a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal, a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value, and a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.

An integrated circuit device includes dispatcher circuitry that receives signals from a first number of sources, multiplexes the signals into a single mixed signal in a predetermined order, and transmits the mixed signal to a destination via a mixed signal interface having an arbitrary length and operating at an interface clock frequency equal to a product of a device clock frequency and the first number. A second number of samplers is disposed in series along the mixed signal interface, outputting a sampled mixed signal synchronized to the interface clock. A chain of tracking elements in series, corresponding in number to the second number, outputs a tracking indication separate from the sampled mixed signal. Capture circuitry demultiplexes the sampled mixed signal into a plurality of demultiplexed signals, according to a starting point based on the tracking indication, onto a plurality of signal buses corresponding in number to the first number.

A count value generation circuit includes a first counter that counts edges of a reference signal to generate a first count value in synchronization with an input signal, a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal, a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value, and a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.

An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.

An integrated circuit comprising (1) an array of logic tiles including a first and a second plurality of logic tiles, wherein each logic tile of the array is configurable to electrically connect with at least one other logic tile, and (2) a clock mesh fabric to provide a mesh clock signal to the first plurality of the logic tiles. Each logic tile of the first plurality includes clock distribution and transmission circuitry including: (1) tile clock generation circuitry configurable to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals of each logic tile of the first plurality of logic tiles, and (2) clock selection circuitry configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock to the circuitry which performs operations using or based on the associated tile clock.

A count value generation circuit includes a first counter that counts edges of a reference signal to generate a first count value in synchronization with an input signal, a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal, a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value, and a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.

An apparatus for rectifying a resolver output signal may include: a resolver configured to receive an excitation signal and to output a resolver output signal based on the excitation signal, the excitation signal indicating a position of a rotor of a motor; a microprocessor configured to receive a reference rectification signal generated by rectification of the excitation signal and to output a delay signal by delaying the reference rectification signal according to a preset value; and a delay amount detection circuit configured to receive a reference excitation signal generated by rectification of the resolver output signal, to receive the delay signal from the microprocessor, to compare the reference excitation signal with the delay signal, and to output a phase difference detection signal and a delay amount excess/shortage signal to the microprocessor.