An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.

A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.

A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current I.sub.ref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current I.sub.ref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.

A phase locked loop circuit includes a voltage controlled oscillator configured to output a clock signal having a predetermined frequency based in a control voltage, a phase frequency detector configured to compare the clock signal with a reference signal to output a first control signal and a second control signal, a charge pump configured to output the control voltage based on the first control signal and the second control signal, a voltage supply including an output terminal connected to an output terminal of the charge pump by a transmission switch, and a leakage remover circuit connected to the transmission switch and configured to remove a leakage current flowing through the transmission switch while the transmission switch is turned-off.

A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

A non-linear charge pump for phased lock loops. Furthermore, an auxiliary charge pump apparatus, comprising a positive switch electrically connected to a current source configured to supplement power to a charge pump, a negative switch electrically connected to a current sink configured to discharge power from the charge pump, a windowing comparator, further comprising an input signal received from a phase-locked loop, a first comparator configured to compare the input signal against a high voltage threshold, a second comparator configured to compare the input signal against a low voltage threshold, an AND logic gate configured to provide a window signal and an activation circuit electrically connected to the positive switch and negative switch. Additionally, a non-linear charge pump system and method for reacquiring frequency lock of a phase lock loop.

A non-linear charge pump for phased lock loops. Furthermore, an auxiliary charge pump apparatus, comprising a positive switch electrically connected to a current source configured to supplement power to a charge pump, a negative switch electrically connected to a current sink configured to discharge power from the charge pump, a windowing comparator, further comprising an input signal received from a phase-locked loop, a first comparator configured to compare the input signal against a high voltage threshold, a second comparator configured to compare the input signal against a low voltage threshold, an AND logic gate configured to provide a window signal and an activation circuit electrically connected to the positive switch and negative switch. Additionally, a non-linear charge pump system and method for reacquiring frequency lock of a phase lock loop.

A clock generator circuit includes a charge pump unit, a low-pass filter unit, a current-controlled clock generator and a voltage-to-current converter unit. The charge pump unit provides a pump current at an output terminal thereof. The low-pass filter unit is coupled to the output terminal of the charge pump unit, and develops a control voltage at an output terminal thereof based on the pump current. The voltage-to-current converter unit is coupled to the output terminal of the low-pass filter unit, the current-controlled clock generator and the charge pump unit, and provides a control current to the current-controlled clock generator. Each of the low-pass filter unit and the voltage-to-current converter unit includes a resistive element.

Charge pump circuitry comprises a differential amplifier and parallel-connected reference, auxiliary and output current paths comprising first current-mirror transistors connected so an auxiliary current and a first output current along a first part of the output current path are dependent on the reference current. The auxiliary and output current paths comprise second-current-mirror transistors connected so a second output current flowing along a second part of the output current path is dependent on the auxiliary current. The auxiliary current path comprises a control transistor connected in series with the first-current-mirror transistor of that path. The differential amplifier receives first and second input signals from nodes in the auxiliary and output current paths, respectively, and controls the control transistor with its amplifier output signal to control the drain or collector voltage of the first-current mirror transistor in the auxiliary path.