Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.

A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.

The present disclosure relates to a phase-lock-loop, which includes a phase detector (PD), a charge pump (CP), a sampled lowpass filter structure, and a voltage-controlled oscillator (VCO) structure. The PD is configured to receive a RF output signal from the VCO structure and a reference signal, and generate detection signals, which indicate a phase relationship between the RF output signal and the reference signal. The CP is configured to receive the detection signals and generate a CP current. Herein, the CP current flows into or out of the sampled lowpass filter structure based on the detection signals. The sampled lowpass filter is configured to provide an oscillator control voltage, which remains constant within a cycle of the reference signal, to the VCO structure based on the CP current. Based on the oscillator control voltage, the VCO structure is configured to tune the RF output signal.

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

The disclosed embodiments provide various compensated charge pumps (CPs) which have a current mismatch compensation circuitry and various CP output-current-mismatch compensation structures based on using a dummy charge pump (CPdum) and feedback loops. In some embodiments, the CPdum is identically biased as the CP to be compensated. CPdum is configured to sense the CP output voltage and use the feedback loops to generate compensation currents for the CP. The compensation currents simultaneously compensate CP and CPdum. Moreover, CPdum is loaded with high impedance so that the compensation current makes sure CPdum doesn’t have current mismatch. Because CP and CPdum have identical biasings and are compensated in the same manner with the same amount of current, CP output current mismatch is hence effectively eliminated.

Disclosed are a control signal pulse width extraction-based phase-locked acceleration circuit and a phase-locked loop system, the phase-lock acceleration circuit includes a pulse width extraction control circuit and a current injection switch module; the control output terminal of the pulse width extraction control circuit is connected to the current injection control terminal of the current injection switch module, and the stepping current control terminal of the current injection switch module and the driving input terminal of the pulse width extraction control circuit are both connected to the preset control signal output end of a phase frequency detector for use in controlling, according to pulse width changes of signals outputted by the preset control signal output end, the current injection switch module to inject charges until the phases of a reference clock signal and feedback clock signal inputted by the phase frequency detector are synchronized.

An oscillator circuit includes a current source, an oscillating section, a first capacitor, and a setting section. The current source is coupled to a connection node and causes a current having a current value based on an input voltage to flow from a first power node to the connection node. The oscillating section is on a current path between the connection node and a second power node. The oscillating section oscillates at an oscillation frequency based on a current flowing through the current path. The first capacitor is between the connection node and the second power node. The first capacitor has a capacitance that varies in accordance with a voltage at the connection node. The setting section that performs variation operation based on the voltage at the connection node. The variation operation is operation of varying an impedance between the connection node and the second power node.

In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.