A phase-locked loop (PLL) and a method for calibrating a VCO therein are provided. The PLL comprises a frequency-phase detector, a charge pump, a loop filter, a VCO, a divider and a calibration circuit. The calibration circuit is used to acquire a frequency of an output signal of the VCO, to calibrate the frequency of the output signal according to an expected frequency, and to acquire frequency control parameters of the VCO at the current signal frequency. The amplitude and gain of the output signal are kept constant according to the amplitude control parameters and gain control parameters. The PLL can meet the demands on frequencies of multiple protocols and can adaptively look up and stabilize the suitable frequency. It solves the issue that the amplitude of the output signal of the VCO is not constant when the PLL operates in a large frequency range.

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.

In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

A system for generating an RFPWM signal comprises a delta sigma modulator having a plurality of outputs, a phase-locked loop comprising a plurality of phase quantization outputs, at least one multiplexer having a plurality of signal inputs, a plurality of selector inputs, and at least one output, the signal inputs communicatively connected to the phase quantization outputs of the phase-locked loop and the selector inputs electrically connected to the outputs of the delta sigma modulator, and a driver having an input communicatively connected to the output of the multiplexer and an output generating an RFPWM signal. A method of generating an RFPWM signal is also described.

A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.

A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

The present disclosure relates to a phase-lock-loop, which includes a phase detector (PD), a charge pump (CP), a sampled lowpass filter structure, and a voltage-controlled oscillator (VCO) structure. The PD is configured to receive a RF output signal from the VCO structure and a reference signal, and generate detection signals, which indicate a phase relationship between the RF output signal and the reference signal. The CP is configured to receive the detection signals and generate a CP current. Herein, the CP current flows into or out of the sampled lowpass filter structure based on the detection signals. The sampled lowpass filter is configured to provide an oscillator control voltage, which remains constant within a cycle of the reference signal, to the VCO structure based on the CP current. Based on the oscillator control voltage, the VCO structure is configured to tune the RF output signal.

An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.