A PLL device includes a voltage control oscillation unit, an analog/digital converter, a quadrature demodulation unit, a comparison signal output unit, a phase difference detection unit, a loop filter, and a digital/analog converter. The quadrature demodulation unit quadrature-demodulates the digital feedback signal to obtain an in-phase component (I component) and a quadrature-phase component (Q component). The comparison signal has a set frequency of the output signal when the feedback signal is the output signal and has a frequency obtained by dividing the set frequency by the dividing number when the feedback signal is the frequency division signal. The phase difference detection unit obtains a phase difference between the digital feedback signal and the digital comparison signal based on the I component and the Q component of the digital feedback signal and the I component and an Q component of a comparison signal.

A PLL device includes a voltage control oscillation unit, an analog/digital converter, a quadrature demodulation unit, a comparison signal output unit, a phase difference detection unit, a loop filter, and a digital/analog converter. The quadrature demodulation unit quadrature-demodulates the digital feedback signal to obtain an in-phase component (I component) and a quadrature-phase component (Q component). The comparison signal has a set frequency of the output signal when the feedback signal is the output signal and has a frequency obtained by dividing the set frequency by the dividing number when the feedback signal is the frequency division signal. The phase difference detection unit obtains a phase difference between the digital feedback signal and the digital comparison signal based on the I component and the Q component of the digital feedback signal and the I component and an Q component of a comparison signal.

A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

An apparatus includes a time-to-digital converter (TDC). The TDC includes a fine TDC (F-TDC) to generate a first output signal in a first range in response to a first signal and a second signal, and a coarse TDC (C-TDC) to generate a second output signal in a second range in response to the first signal and a delayed version of the second signal.

A PLL device includes a voltage control oscillation unit, an analog/digital converter, a quadrature demodulation unit, a comparison signal output unit, a phase difference detection unit, a loop filter, and a digital/analog converter. The quadrature demodulation unit quadrature-demodulates the digital feedback signal to obtain an in-phase component (I component) and a quadrature-phase component (Q component). The comparison signal has a set frequency of the output signal when the feedback signal is the output signal and has a frequency obtained by dividing the set frequency by the dividing number when the feedback signal is the frequency division signal. The phase difference detection unit obtains a phase difference between the digital feedback signal and the digital comparison signal based on the I component and the Q component of the digital feedback signal and the I component and an Q component of a comparison signal.

A PLL device includes a voltage control oscillation unit, an analog/digital converter, a quadrature demodulation unit, a comparison signal output unit, a phase difference detection unit, a loop filter, and a digital/analog converter. The quadrature demodulation unit quadrature-demodulates the digital feedback signal to obtain an in-phase component (I component) and a quadrature-phase component (Q component). The comparison signal has a set frequency of the output signal when the feedback signal is the output signal and has a frequency obtained by dividing the set frequency by the dividing number when the feedback signal is the frequency division signal. The phase difference detection unit obtains a phase difference between the digital feedback signal and the digital comparison signal based on the I component and the Q component of the digital feedback signal and the I component and an Q component of a comparison signal.

A circuit device includes a phase comparison circuit that performs phase comparison between a reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage, a voltage controlled oscillation circuit that generates a clock signal, a dividing circuit that divides the clock signal and outputs the feedback clock signal, a processing circuit that sets a division ratio of the dividing circuit, a first register in which slope information of a waveform signal for spreading the frequency of the clock signal is set, and a second register in which amplitude information of the waveform signal is set. The processing circuit generates a waveform signal value based on the slope information and the amplitude information set in the first and second registers, and outputs division ratio data based on the waveform signal value and the division ratio setting value to the dividing circuit.