An integrated circuit apparatus includes an oscillation circuit that generates an oscillation signal by using a resonator, an output buffer circuit that outputs a clock signal based on the oscillation signal, a DC voltage generation circuit that generates a DC voltage used to generate the oscillation signal or the clock signal, a power source pad to which a power source voltage is supplied, a ground pad to which a ground voltage is supplied, and a clock pad via which the clock signal is outputted. The ground pad and the DC voltage generation circuit are disposed so as to overlap with each other in the plan view.

An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the jth stage is configured to receive as an input the sum of the error of the preceding stage and a high amplitude dither signal derived from the error of the kth stage, where 1≤j≤k≤L.

A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

A phase locked loop device may include: a frequency modulating circuit configured to output a reference signal obtained by multiplying a frequency of an input signal by a predetermined ratio based on the input signal; a sigma-delta modulator configured to output division ratio information on one of a plurality of division rates at a number of times proportional to a frequency of the reference signal; and a phase locked loop (PLL) circuit configured to determine whether to activate based on a command signal, and, when activated, perform a phase-locking operation based on a fractional division based on the reference signal and the division ratio information.

There is configured a charge pump circuit for outputting a phase difference current to a first node, the charge pump circuit including a first current source coupled between a high potential power supply node and the first node, a second current source coupled between a low potential power supply node and the first node, a first switch coupled between the first current source and the first node, a second switch coupled between the second current source and the first node, a third switch coupled between the first current source and a second node, a fourth switch coupled between the second current source and the second node, a third current source for supplying a negative offset current to the first node, and a push-type differential amplifier circuit an input side of which is coupled to the first node, and an output side of which is coupled to the second node.

In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

Disclosed herein are systems and methods for improved performance of phase-locked loop based clock generators, particularly in the context of wireless audio. A PLL clock generator includes a PLL core configured to receive a module reference clock provided by a communications module and generate a subsystem data clock corresponding to a module data clock of the communications module; and a data clock tracker module configured to receive the module data and subsystem data clocks and determine a corresponding data clock correction factor. The bandwidth of the PLL core may be dynamically changed thereby enabling both fast and very precise settling. The PLL core may use a low jitter frequency reference for the phase detector while an a synchronous and jitter-prone audio sample clock is used to ensure a mean frequency of the PLL core tracks the audio sample clock.

An automatic frequency calibration and lock detection circuit includes a frequency error generator circuit, an automatic frequency calibration signal generator circuit, and a lock flag generator circuit. The frequency error generator circuit generates a frequency error signal based on a reference frequency signal and an output frequency signal. The frequency error signal represents a difference between a frequency of the output frequency signal and a target frequency. The automatic frequency calibration signal generator circuit generates an automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal. The lock flag generator circuit generates a lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal. The frequency error generator circuit is shared by the automatic frequency calibration signal generator circuit and the lock flag generator circuit.