A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when a rollover event of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to a VCO clock cycle phase fraction value when the rollover detector circuit has detected the interpolator rollover event.

A method of generating power with a power generation system. Solid state generators generate a plurality of outputs. The outputs of the solid state generator modules are combined from a plurality of channels, in a combiner, using a phase optimization technique to generate an in phase combined output power.

In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.

In one embodiment, a spread spectrum clock generator, comprising a digital delta sigma modulator coupled to a fractional N, phase locked loop (PLL), the PLL comprising a discrete-time capacitance multiplier loop filter, the discrete-time capacitance multiplier loop filter comprising: an amplifier comprising a non-inverting input and an inverting input; a first switched capacitor resistor and a capacitor coupled to the non-inverting input, the capacitor coupled between the first switched capacitor resistor and the non-inverting input; and a second switched capacitor resistor coupled to the inverting input.

A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.