A digital-to-analog converter (DAC) device includes a DAC circuitry, a calibration circuitry, and a randomization circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to least significant bits of an input signal. The second DAC circuit is configured to output a second signal. The calibration circuitry is configured to compare the first signal with the second signal, in order to calibrate the second DAC circuit. The randomization circuitry is configured to randomize most significant bits of the input signal, in order to generate first control signals, in which the second DAC circuit is further configured to generate the second signal according to the most significant bits or the first control signals.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.

A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by r.sub.i bit positions for the i-th second digital control code, wherein r.sub.i is an integer smaller than N?1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

The present disclosure provides an output conversion circuit and a fingerprint identification system. The output conversion circuit includes: a comparator, a counter, and a reference signal generator, where the comparator includes: a first input end, configured to receive a first output signal; a second input end; and an output end, configured to generate a comparison output signal; the counter is connected to the output end of the comparator, and configured to generate a second output signal; and the reference signal generator is connected to the second input end, and configured to generate a reference signal, where the reference signal generator includes a random digit generator configured to generate a random digit, and the reference signal is associated with the random digit; where the comparator generates the comparison output signal according to the first output signal and the reference signal.

In a general aspect, an apparatus can include a signal analyzer configured to analyze a signal associated with a processing pipeline, and a dynamic element matching (DEM) selection module configured to select a DEM algorithm from a plurality of DEM algorithms based on the analysis performed by the signal analyzer. The apparatus can include a set of circuit elements where each circuit element from the set of circuit elements has the same logical configuration, and a circuit element selection module configured to select a subset of the set of circuit elements based on the selected DEM algorithm.

A sigma delta modulator includes an integrator, a quantizer, a randomization circuit, and a digital to analog converter circuit. The integrator is configured to integrate an analog signal, in order to generate a first signal, in which the analog signal is a sum of an input signal and a second signal. The quantizer is coupled to the integrator and configured to quantize the first signal to generate a digital signal which has a plurality of bits. The randomization circuit is coupled to the quantizer, and is configured to randomize partial bits in the plurality of bits of the digital signal, in order to generate first control signals. The digital to analog converter (DAC) circuit is coupled to the quantizer and the randomization circuit, and is configured to generate the second signal according to the first control signals and remaining bits in the plurality of bits of the digital signal.

Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.

A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.