This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit (200) receives an analogue input signal (S.sub.IN) and outputs a digital output signal (S.sub.OUT). The circuit has a sampling capacitor (101), a controlled oscillator (104) and a counter (106) for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor (102) is coupled to an input node for the input signal, e.g. via switch (102a). In the read-out phase, the sampling capacitor is coupled to the controlled oscillator (104), e.g. via switch (102b), such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) coupled to receive a first input voltage to generate a first output voltage; a second DAC coupled to receive a second input voltage to generate a second output voltage; a comparator having a positive input node coupled to receive the first output voltage of the first DAC, and a negative input node coupled to receive the second output voltage of the second DAC; a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; a first calibration circuit coupled between the positive input node of the comparator and a ground voltage; and a second calibration circuit coupled between the negative input node of the comparator and the ground voltage.

A passive conjunction circuit for an analog-to-digital converter (ADC) is disclosed. In one aspect, the passive conjunction circuit includes a first input node receiving an analog input signal to be converted by the ADC and a second input node receiving a reference voltage other than a ground voltage of the ADC. The passive conjunction circuit also includes a first output node to be connected to a first differential input of the ADC (20) and a second output node to be connected to a second differential input of the ADC. The passive conjunction circuit further includes a first voltage divider interconnected between the first input and output nodes and a second voltage divider interconnected between the second input and output nodes.

A pseudo differential analog-to-digital converter includes: a first capacitor array and a second capacitor array respectively coupled to input terminals of an analog-to-digital circuit; where an output terminal of the first capacitor array receives a first reference voltage, and an output terminal of the second capacitor array receives a second reference voltage; and where a difference between the first and second reference voltages is set between zero and a peak value of an analog input signal.

The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.

A passive conjunction circuit for an analog-to-digital converter (ADC) is disclosed. In one aspect, the passive conjunction circuit includes a first input node receiving an analog input signal to be converted by the ADC and a second input node receiving a reference voltage other than a ground voltage of the ADC. The passive conjunction circuit also includes a first output node to be connected to a first differential input of the ADC (20) and a second output node to be connected to a second differential input of the ADC. The passive conjunction circuit further includes a first voltage divider interconnected between the first input and output nodes and a second voltage divider interconnected between the second input and output nodes.

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C.sub.n[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator V.sub.d and the digital output port.

A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output includes a first capacitor digital-to-analog (DAC) and a second capacitor DAC. One of the first capacitor DAC and the second capacitor DAC that has greater output signal is defined as a higher-voltage capacitor DAC, and the other as an un-switching capacitor DAC. In an m-th conversion phase, an (m1)-th capacitor of the un-switching capacitor DAC is switched according to a comparison between output signals of the higher-voltage capacitor DAC and the un-switching capacitor DAC.